EPF10K100B Device Datasheet

EPF10K100B Datasheet, PDF, Equivalent


Part Number

EPF10K100B

Description

Embedded Programmable Logic Device

Manufacture

Altera Corporation

Total Page 1 Pages
Datasheet
Download EPF10K100B Datasheet


EPF10K100B
July 1998, ver. 1
Preliminary
Information
www.DataSheet4U.com
EPF10K100B
Embedded Programmable
®
Logic Device
Errata Sheet
This errata sheet provides updated information for Revision A and
Revision B EPF10K100B devices. The die revision is indicated by the third
digit of the nine-digit code on the top side of the device. Revision C and
higher EPF10K100B devices do not exhibit the conditions described in this
document.
Under certain voltage conditions, the output buffer delay for Revision A
and Revision B EPF10K100B devices is slower than the reported value for
I/O pins with the Slow Slew Rate option turned on in the MAX+PLUS® II
software. The MAX+PLUS II version 9.0 Timing Analyzer and Simulator
report an added output delay of 4.5 ns when the Slow Slew Rate option is
turned on. When the Slow Slew Rate option is turned on and the VCCINT
and VCCIO pins are powered at 2.3 V and 3.6 V, respectively, the change
in the measured output buffer delay due to the Slow Slew Rate option
may be as high as 7.5 ns.
This condition in which the VCCINT and VCCIO pins are powered to the
opposite extremes is rare. For designs where this increased delay is a
problem, you should either turn off the Slow Slew Rate option or adjust
the circuit’s power supply to provide a 2.5-V VCCINT.
With the Slow Slew Rate option turned off, the device functions as
reported in the MAX+PLUS II version 9.0 Timing Analyzer and
Simulator.
®
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Altera, EPF10K100B, MAX, MAX+PLUS, and MAX+PLUS II are trademarks and/or service marks of Altera
Corporation in the United States and other countries. Altera acknowledges the trademarks of other
organizations for their respective products or services mentioned in this document. Altera products are
protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and
copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance
with Altera’s standard warranty, but reserves the right to make changes to any products and services at any
time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by
Altera Corporation. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for
products or services.
Copyright © 1998 Altera Corporation. All rights reserved.
Altera Corporation
A-ES-10K100B-1.0
1


Features EPF10K100B ® Embedded Programmable Log ic Device Errata Sheet July 1998, ver. 1 Preliminary Information This errat a sheet provides updated information fo r Revision A and Revision B EPF10K100B devices. The die revision is indicated by the third digit of the nine-digit co de on the top side of the device. Revis ion C and higher EPF10K100B devices do not exhibit the conditions described in this document. Under certain voltage c onditions, the output buffer delay for Revision A and Revision B EPF10K100B de vices is slower than the reported value for I/O pins with the Slow Slew Rate o ption turned on in the MAX+PLUS® II so ftware. The MAX+PLUS II version 9.0 Tim ing Analyzer and Simulator report an ad ded output delay of 4.5 ns when the Slo w Slew Rate option is turned on. When t he Slow Slew Rate option is turned on a nd the VCCINT and VCCIO pins are powere d at 2.3 V and 3.6 V, respectively, the change in the measured output buffer d elay due to the Slow Slew Rate option may be as high as 7.5 ns. .
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