HI3197

HI3197 Data Sheet October 1998 File Number 4356.1 10-Bit, 125 MSPS D/A Converter The HI3197 is a high-speed D/A converter which can perform the multiplexed input of the two system 10-bit data. The maximum conversion rate achieves 125 MSPS. The multiplexed operation is possible by the 1/2 frequencydivided clock or by halving the frequency of the clock with the clock frequency divider circuit having the reset pin in the IC. The data input is TTL; the clock input pin and reset input pin can select either TTL or PECL according to the application. Features Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bits Conversion Rate 125 MSPS (PECL) 100 MSPS (TTL) Data Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TTL Low Power Consumption . . . . . . . . . . . . . . . 400mW (Typ) Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . 1.5pVs Clock, Reset Input Level: TTL and PECL Compatible 2:1 Multiplexed Input Function 1/2 Frequency-Divided Clock Output Possible by the BuiltIn Clock Frequency Divider Circuit Voltage Output (50Ω Load Drive Possible) Single Power Supply or ±Dual Power Supplies Polarity Switching Function of Reset Signal Ordering Information PART NUMBER HI3197JCQ TEMP. RANGE (oC) -20 to 75 PACKAGE 48 Ld MQFP/ PQFP PKG. NO. Q48.7x7-S Applications LCD DDS HDTV Communications (QPSK, QAM) www.DataSheet4U.com Pinout HI3197 (MQFP) TOP VIEW AOUTN AGND2 AOUTP AVCC2 DGND2 AVCC0 DVCC2 V...