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SST45VF020 Dataheets PDF



Part Number SST45VF020
Manufacturers SST
Logo SST
Description (SST45VFxxx) 512 Kbit / 1 Mbit / 2 Mbit Serial Flash
Datasheet SST45VF020 DatasheetSST45VF020 Datasheet (PDF)

512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020 Advance Information FEATURES: • Single 2.7-3.6V Read and Write Operations • Serial Interface Architecture – SPI Compatible: Mode 0 and Mode 3 • Byte Serial Read with Single Command • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 20 mA (typical) – Standby Current: 10 µA (typical) • Sector or Chip-Erase Capability – Uniform 4 .

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512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020 Advance Information FEATURES: • Single 2.7-3.6V Read and Write Operations • Serial Interface Architecture – SPI Compatible: Mode 0 and Mode 3 • Byte Serial Read with Single Command • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 20 mA (typical) – Standby Current: 10 µA (typical) • Sector or Chip-Erase Capability – Uniform 4 KByte sectors • Fast Erase and Byte-Program: – Chip-Erase Time: 70 ms (typical) – Sector-Erase Time: 18 ms (typical) – Byte-Program Time: 14 µs (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Software Status • 10 MHz Max Clock Frequency • Hardware Reset Pin (RESET#) – Resets the device to Standby Mode • CMOS I/O Compatibility • Hardware Data Protection – Protects and unprotects the device from Write operation • Packages Available – 8-Pin SOIC (4.9mm x 6mm) 1 2 3 4 5 6 7 www.DataSheet4U.com PRODUCT DESCRIPTION The SST45VF512, SST45VF010 and SST45VF020 are manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The Serial Flash is organized as 16 sectors of 4096 Bytes for SST45VF512, 32 sectors of 4096 Bytes for the SST45VF010 and 64 sectors of 4096 Bytes for the SST45VF020. The memory is accessed for Read or Erase/Program by the SPI bus compatible serial protocol. The bus signals are: serial data input (SI), serial data output (SO), serial clock (SCK), write protect (WP#), chip enable (CE#), and hardware reset (RESET#). The SST45VFxxx devices are offered in 8-pin SOIC package. See Figure 1 for the pinout. Device Operation The SST45VFxxx uses bus cycles of 8 bits each for commands, data, and addresses to execute operations. The operation instructions are listed in Table 2. All instructions are synchronized off a high to low transition of CE#. The first low to high transition on SCK will initiate the instruction sequence. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. Any low to high transition on CE# before the input instruction completes will terminate any instruction in progress and return the device to the standby mode. Read The Read operation outputs the data in order from the initial accessed address. While SCK is input, the address will be incremented automatically until end (top) of the address space, then the internal address pointer automatically increments to beginning (bottom) of the address space (00000H), and data out stream will continue. The read data stream is continuous through all addresses until terminated by a low to high transition on CE#. Sector/Chip-Erase Operation The Sector-Erase operation clears all bits in the selected sector to “FF”. The Chip-Erase instruction clears all bits in the device to “FF”. Byte-Program Operation The Byte-Program operation programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (“FF”) when initiating a Program operation. The data is input from bit 7 to bit 0 in order. Software Status Operation The Status operation determines if an Erase or Program operation is in progress. If bit 0 is at a “0” an Erase or Program operation is in progress, the device is busy. If bit 0 is at a “1” the device is ready for any valid operation. The status read is continuous with ongoing clock cycles until terminated by a low to high transition on CE#. 8 9 10 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 514-1 10/00 S71178 1 512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020 Advance Information Reset Reset will terminate any operation, e.g., Read, Erase and Program, in progress. It is activated by a high to low transition on the RESET# pin. The device will remain in reset condition as long as RESET# is low. Minimum reset time is 10µs. See Figure 14 for reset timing diagram. RESET# is internally pulled-up and could remain unconnected during normal operation. After reset, the device is in standby mode, a high to low transition on CE# is required to start the next operation. An internal power-on reset circuit protects against accidental data writes. Applying a logic level low to RESET# during the power-on process then changing to a logic level high when VDD has reached the correct voltage level will provide additional protection against accidental writes during power on. Read SST ID/Read Device ID The Read SST ID and Read Device ID operations read the JEDEC assigned manufacturer identification and the manufacturer assigned device identification codes. These codes may be used to determine the actual device resident in the system. FUNCTIONAL BLOCK DIAGRAM TABLE 1: PRODUCT IDENTIFICATION Manufacturer’s ID Device ID SST45VF512 SST45VF010 SST45VF020 B.


SST45VF512 SST45VF020 STD13003Q


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