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IS42S16800B Dataheets PDF



Part Number IS42S16800B
Manufacturers ISSI
Logo ISSI
Description 8Meg x16 128-MBIT SYNCHRONOUS DRAM
Datasheet IS42S16800B DatasheetIS42S16800B Datasheet (PDF)

IS42S81600B IS42S16800B 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM ISSI MAY 2006 ® FEATURES • Clock frequency: 167, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS42S81600B IS42S16800B • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) www.DataSheet4U.com OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and.

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IS42S81600B IS42S16800B 16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM ISSI MAY 2006 ® FEATURES • Clock frequency: 167, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS42S81600B IS42S16800B • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) www.DataSheet4U.com OVERVIEW ISSI's 128Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.The 128Mb SDRAM is organized as follows. VDDQ VDD 3.3V 3.3V 3.3V 3.3V IS42S81600B 4M x8x4 Banks 54-pin TSOPII IS42S16800B 2M x16x4 Banks 54-pin TSOPII • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh with programmable refresh periods • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Industrial Temperature Availability • Lead-free Availability KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 6 – 167 – 5.4 – -7 7 10 143 100 5.4 6 -75E – 7.5 – 133 – 6 Unit ns ns Mhz Mhz ns ns Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 1 IS42S81600B, IS42S16800B ISSI ® DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V VDD and 3.3V VDDQ memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 128Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, followed by a READ or WRITE command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option. FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY) www.DataSheet4U.com CLK CKE CS RAS CAS WE DQML DQMH COMMAND DECODER & CLOCK GENERATOR DATA IN BUFFER 16 16 2 MODE REGISTER 12 REFRESH CONTROLLER DQ 0-15 SELF REFRESH CONTROLLER A10 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BA0 BA1 12 DATA OUT BUFFER 16 16 VDD/VDDQ Vss/VssQ REFRESH COUNTER 4096 4096 4096 4096 ROW DECODER MULTIPLEXER MEMORY CELL ARRAY 12 ROW ADDRESS LATCH 12 ROW ADDRESS BUFFER BANK 0 SENSE AMP I/O GATE COLUMN ADDRESS LATCH 9 512 (x 16) BANK CONTROL LOGIC BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 9 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. E 05/01/06 IS42S81600B, IS42S16800B ISSI ® PIN CONFIGURATIONS 54 pin TSOP - Type II for x8 VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE CAS RAS CS www.DataSheet4U.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS BA0 BA1 A10 A0 A1 A2 A3 VDD PIN DESCRIPTIONS A0-A11 A0-A9 BA0, BA.


AS212-93 IS42S16800B IS42S81600B


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