LP61L1008

LP61L1008 Series 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM Document Title 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM Revision History Rev. No. 2.0 History Add Product Family and 32-pin sTSOP (Type I) package Issue Date June 11, 2002 Remark (June, 2002, Version 2.0) AMIC Technology, Inc. LP61L1008 Series 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM Features n Single 3.3V ± 10% power supply n Access times: 12/15 ns (max.) n Current: Operating: 180mA (max.) Standby: 5mA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Center Power/Ground Pin Configuration n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2.0V (min.) n Available in 32-pin SOJ 300 mil and 32-pin sTSOP packages General Description The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Product Family LP61L1008 Operating Temperature 0°C~70°C VCC Range 3.0V~3.6V Power Dissipation Speed 12/15 ns Data Retention (ICCDR,...