Interface Module. EPA2013DG Datasheet

EPA2013DG Module. Datasheet pdf. Equivalent

Part EPA2013DG
Description 10 Base-T Interface Module
Feature www.DataSheet4U.com 10 Base-T Interface Module EPA2013DG ELECTRONICS INC. • General Purpose 10 Ba.
Manufacture PCA ELECTRONICS
Datasheet
Download EPA2013DG Datasheet



EPA2013DG
www.DataSheet4U.com
ELECTRONICS INC.
10 Base-T Interface Module
EPA2013DG
• General Purpose 10 Base-T Filter Module •
• Available in SMD and DIP Packages •
• Complies with or exceeds IEEE 802.3, 10 Base-T Requirements •
Cut-off
Frequency
(MHz)
Insertion
Loss
(dB Max.)
Return
Loss
(dB Min.)
Electrical Parameters @ 25° C
Attenuation
(dB Min.)
Common Mode
Rejection
(dB Min.)
Crosstalk
(dB Min.)
± 1.0
MHz
1-10
MHz
5-10
MHz
@ 20
MHz
@ 25
MHz
@ 30
MHz
@ 40
MHz
@ 50
MHz
@ 100
MHz
@ 200
MHz
@ 1-10
MHz
Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv Xmit Rcv
17 17 -1 -1 -15 -15 -7 -6 -19 -14 -30 -20 -35 -31 -30 --- -25 --- --- --- -30 -30
Isolation : meets or exceeds 802.3 IEEE Requirements • Characteristic Filter Impedance : 100
• *Referenced to the Output Level Fundamental Frequency @ 5 MHz •
Transmit Channel
Schematic
Receive Channel
1
2 LPF
3
1:1
Pin 1
I.D.
Package
A
(J) M
PCA
EPA2013DG
Date Code
B
Q
16
14
15
N
Pad
Layout
P
D
E
C
HF
R
K
L
G
I
6
LPF 7
11
10
89
1:1
Dim.
A
B
C
D
E
F
G
H
I
(J)
K
L
M
N
P
Q
R
Dimensions
(Inches)
(Millimeters)
Min. Max. Nom. Min. Max. Nom.
.980 1.00
24.89 25.4
.260 .280
6.60 7.11
.255 .275
6.48 6.99
.700 Typ.
17.78 Typ.
.005 .015
.127 .381
.100 Typ.
2.54 Typ.
.380 .400
9.65 10.16
.016 .022
.406 .559
.008 .012
.203 .305
.145 Typ.
3.91 Typ.
0° 8°
0° 8°
.025 .045
.635 1.14
.030 .762
.100 2.54
.055 1.40
.410 10.41
.300 Typ.
7.62 Typ.
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
CSA2013DGa Rev. Orig. 5/23/97
Product performance is limited to specified parameters. Data is subject to change without prior notice.
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pca.com



EPA2013DG
ELECTRONICS INC.
10 Base-T Interface Module
EPA2013DG
The circuit below is a guideline for interconnecting PCA’s EPA2013DG with a typical 10 Base-T PHY chip over UTP cable.
Further details of system design, such as chip pin-out, etc. can be obtained from the specific chip manufacturer.
Typical insertion loss of the isolation transformer/filter is 0.7dB. This parameter covers the entire spectrum of the encoded
signals in 10 Base-T protocols. However, the predistortion resistor network introduces some loss which has to be taken
into account in determining how well your design meets the Standard Template requirements. Additionally, the following
need to be considered while selecting resistor values :
a. The filter needs 100termination, thus the Thevenin’s equivalent resistance seen by the filter looking into the transmit
outputs from the chip must be equal to a value close to 100. The typical driver output impedance is 5. Thus
choose R1 and R2 values that are lowered by 5on each leg. Following these guidelines will guarantee that the
return loss specifications are satisfied at all extremes of cable impedance (i.e. 85to 115) while the module is
installed in your system.
b. That the template requirements are satisfied under the worst case Vcc (i.e. 4.5V), will impose a further constraint on
resistor selection, in that they ought to be the minimum derived from the calculations. Add R3 for more flexibility in
setting voltage levels at the outputs.
Note that some systems have auto polarity detection and some do not. If not, be certain to follow the proper polarity.
It is recommended that system designers ground the chip side center taps via a low voltage capacitor. Taking the cable
side center taps to chassis via capacitors, is not recommended, as this will add cost without containing EMI. This may
worsen EMI, specifically if the primary “common mode termination” is pulled to ground as shown.
The pulldown resistors used around the RJ45 connector have been known to suppress unwanted radiation that unused
wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is
finalized.
It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit
the plane off at least 0.08 inches away from the chip side pins of EPA2013DG. There need not be any ground plane
beyond this point.
For best results, PCB designer should design the outgoing traces preferably to be 50, balanced and well coupled to
achieve minimum radiation from these traces.
Typical Application Circuit for UTP with external Resistor Network
TX+
TXd+
R1
R2
TX-
10 Base-T TXd-
PHY
RX+
R1
R2
16
1 14
2 11
39
EPA2013DG
67 8
TX+
1
TX-
2
3 RX+
RJ45*
6 RX-
4578
RX-
Notes : * Pin-outs shown are for NIC configurations.
For Hubs and Repeaters swap pins 1-2 with pins 3-6.
Chassis
Ground
PCA ELECTRONICS, INC.
16799 SCHOENBORN ST.
NORTH HILLS, CA 91343
CSA2013DGb Rev. Orig. 5/23/97
TEL: (818) 892-0761
FAX: (818) 894-5791
http://www.pca.com





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