A3P125

www.DataSheet4U.com Advanced v0.2 ™ ProASIC3 Flash Family FPGAs Features and Benefits High Capacity 30 k to 1 Million System Gates Up to 144 kbits of True Dual-Port SRAM Up to 288 User I/Os 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live-At-Power-Up Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off 1 kbit of FlashROM (FROM) 150+ MHz Internal System Performance with 3.3 V, 66 MHz 64-bit PCI (except A3P030) Up to 350 MHz External System Performance Secure ISP Using On-Chip 128-Bit AES Decryption via JTAG (IEEE1532-compliant) (except A3P030) FlashLock™ to Secure FPGA Contents 1.5 V Core Voltage for Low Power Support for 1.5-V-Only Systems Low-Impedance Flash Switches Segmented, Hierarchical Routing and Clock Structure Ultra-Fast Local and Long-Line Network Enhanced High-Speed, Very Long-Line Network High-Performance, Low-Skew Global Network Architecture Supports Ultra-High Utilization Advanced I/O 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above) 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages – Up to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except A3P030), and LVCMOS 2.5 V / 5.0 V Input Differential I/O Standards: LVPECL and LVDS (A3P250 and above) I/O Registers on Input, Output, and Enable Paths Hot-Swappable I/Os (A3P030 only) Programmable Output Slew Rate a...