FLASH MEMORY. MB84VD21191EM-70 Datasheet

MB84VD21191EM-70 MEMORY. Datasheet pdf. Equivalent

Part MB84VD21191EM-70
Description (MB84VD2118xEM-70 / MB84VD2119xEM-70) Stacked MCP (Multi-Chip Package) FLASH MEMORY
Feature www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-50307-1E Stacked MCP (Multi-Chip Packag.
Manufacture SPANSION
Datasheet
Download MB84VD21191EM-70 Datasheet



MB84VD21191EM-70
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50307-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (×8/×16) FLASH MEMORY &
4M (×8/×16) STATIC RAM
MB84VD2118XEM-70/MB84VD2119XEM-70
s FEATURES
• Power Supply Voltage of 2.7 V to 3.3 V
High Performance
70 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
Operating Temperature
–40 °C to +85 °C
• Package 56-ball FBGA
(Continued)
s PRODUCT LINE-UP
Part No.
Supply Voltage(V)
Max Address Access Time (ns)
MB84VD2118XEM/MB84VD2119XEM
VCCf*=
3.0
V
+0.3 V
–0.3 V
VCCs*=
3.0
V
+0.3V
–0.3 V
70 70
Max CE Access Time (ns)
70 70
Max OE Access Time (ns)
30 35
*: Both VCCf and VCCs must be in recommended operation range when either part is being accessed.
s PACKAGE
56-ball plastic FBGA
(BGA-56P-M02)



MB84VD21191EM-70
MB84VD2118XEM/2119XEM-70
(Continued)
FLASH MEMORY
Simultaneous Read/Write Operations (Dual Bank)
Miltiple devices available with different bank sizes (Please refer to ORDERING INFORMATION)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
Sector Erase Architecture
Eight 4 K words and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
MB84VD2118XEM: Top sector
MB84VD2119XEM: Bottom sector
Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion
Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
Low VCC Write Inhibit 2.5 V
HiddenROM Region
64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC Input Pin
At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2118XEM:SA37,SA38 MB84VD2119XEM:SA0,SA1)
At VIH, allows removal of boot sector protection
At VACC, program time will reduse by 40%.
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL16XTE/BE” Datasheet in Detailed Function
SRAM
Power Dissipation
Operating : 40 mA Max
Standby : 10 µA Max
• Power Down Features using CE1s and CE2s
• Data Retention Supply Voltage: 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte Data Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8)
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
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