16 BIT. MBM29DL164BD Datasheet

MBM29DL164BD BIT. Datasheet pdf. Equivalent

Part MBM29DL164BD
Description (MBM29DL16xTD/BD) FLASH MEMORY CMOS 16M (2M X 8/1M X 16) BIT
Feature www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20874-7E FLASH MEMORY CMOS 16M (2M × 8.
Manufacture Fujitsu Media Devices
Total Page 30 Pages
Datasheet
Download MBM29DL164BD Datasheet



MBM29DL164BD
www.DataSheet4U.com
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20874-7E
FLASH MEMORY
CMOS
16M (2M × 8/1M × 16) BIT Dual Operation
MBM29DL16XTD/BD -70/90
s FEATURES
• 0.33 µm Process Technology
• Simultaneous Read/Write operations (dual bank)
Multiple devices available with different bank sizes (Refer to “MBM29DL16XTD/BD Device Bank Divisions Table”
in sGENERAL DESCRIPTION)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
s PRODUCT LINE UP
(Continued)
Part No.
Ordering Part No.
VCC
=
3.3
V +0.3 V
–0.3 V
VCC
=
3.0
V +0.6 V
–0.3 V
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
MBM29DL16XTD/MBM29DL16XBD
70 —
— 90
70 90
70 90
30 35
s PACKAGES
48-pin plastic TSOP (1)
Marking Side
48-pin plastic TSOP (1)
48-ball plastic FBGA
(FPT-48P-M19)
Marking Side
(FPT-48P-M20)
(BGA-48P-M13)



MBM29DL164BD
MBM29DL16XTD/BD-70/90
(Continued)
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
48-pin TSOP(1) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type)
48-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
Eight 4K word and thirty one 32K word sectors in word mode
Eight 8K byte and thirty one 64K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• HiddenROM region
64K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
• WP/ACC input pin
At VIL, allows protection of boot sectors, regardless of sector group protection/unprotection status
At VACC, increases program performance
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector group protection command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
Temporary sector group unprotection via the RESET pin.
• In accordance with CFI (Common Flash Memory Interface)
* : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
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