16 BIT. MBM29DL323TE Datasheet

MBM29DL323TE BIT. Datasheet pdf. Equivalent

Part MBM29DL323TE
Description (MBM29DL32xTE/BE) FLASH MEMORY CMOS 32 M (4 M X 8/2 M X 16) BIT
Feature www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20881-7E FLASH MEMORY CMOS 32 M (4 M ×.
Manufacture Fujitsu Media Devices
Datasheet
Download MBM29DL323TE Datasheet



MBM29DL323TE
www.DataSheet4U.com
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20881-7E
FLASH MEMORY
CMOS
32 M (4 M × 8/2 M × 16) BIT Dual Operation
MBM29DL32XTE/BE80/90
s DESCRIPTION
The MBM29DL32XTE/BE are a 32 M-bit, 3.0 V-only Flash memory organized as 4 Mbytes of 8 bits each or
2 Mwords of 16 bits each. These devices are designed to be programmed in-system with the standard system
3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also
be reprogrammed in standard EPROM programmers.
MBM29DL32XTE/BE are organized into two banks, Bank 1 and Bank 2, which are considered to be two separate
memory arrays for operations. It is the Fujitsu’s standard 3 V only Flash memories, with the additional capability
of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either
a program or an erase) operation is simultaneously taking place on the other bank.
s PRODUCT LINE UP
(Continued)
Part No.
Power Supply Voltage VCC (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
s PACKAGES
48-pin plastic TSOP (1)
MBM29DL32XTE/BE
80
3.3
+0.3
0.3
80
90
3.0
+0.6
0.3
90
80 90
30 35
48-pin plastic TSOP (1)
63-ball plastic FBGA
Marking Side
(FPT-48P-M19)
Marking Side
(FPT-48P-M20)
(BGA-63P-M01)



MBM29DL323TE
MBM29DL32XTE/BE80/90
(Continued)
In the MBM29DL32XTE/BE, a new design concept is implemented, so called “Sliding Bank Architecture”. Under
this concept, the MBM29DL32XTE/BE can be produced a series of devices with different Bank 1/Bank 2 size
combinations; 4 Mb/28 Mb, 8 Mb/24 Mb, 16 Mb/16 Mb.
To eliminate bus contention the devices have separate chip enable (CE) , write enable (WE) , and output enable
(OE) controls.
The MBM29DL32XTE/BE are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations.
Typically, each sector can be programmed and verified in about 0.5 seconds.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29DL32XTE/BE are erased when shipped from the
factory.
Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector
automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data
Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase
cycle has been completed, the devices internally reset to the read mode.
The MBM29DL32XTE/BE memories electrically erase the entire chip or all bits within a sector simultaneously
via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.
2





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)