BIT MirrorFlashTM. MBM29LV160BM Datasheet
16 M (2M × 8/1M × 16) BIT
The MBM29LV160TM/BM is a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes by 8 bits or 2M words
by 16 bits. The MBM29LV160TM/BM is offered in 48-pin TSOP(1) and 48-ball FBGA. The device is designed to
be programmed in-system with the standard 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for
program or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV160TM/BM offers access times of 90 ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable
(WE), and output enable (OE) controls.
s PRODUCT LINE UP
Max Address Access Time
Max CE Access Time
Max OE Access Time
3.0 V to 3.6 V
48-pin plastic TSOP (1)
48-ball plastic FBGA
* : MirrorFlashTM is a trademark of Fujitsu Limited.
Notes : • Programming in byte mode ( × 8) is prohibited.
• Programming to the address that already contains data is prohibited (It is mandatory to erase data prior to
overprogram on the same address) .
The MBM29LV160TM/BM supports command set compatible with JEDEC single-power-supply EEPROMS stan-
dard. Commands are written into the command register. The register contents serve as input to an internal state-
machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and
data needed for the programming and erase operations. Reading data out of the devices is similar to reading
from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV160TM/BM is programmed by executing the program command sequence. This will invoke the
Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will
invoke the Embedded Erase AlgorithmTM which is an internal algorithm that automatically preprograms the array
if it is not already programmed before executing the erase operation. During erase, the device automatically
times the erase pulse widths and verifies proper cell margin.
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. All sectors are erased when shipped from the factory.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the devices
internally return to the read mode.
Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The devices electrically erase all bits within a sector simulta-
neously via hot-hole assisted erase. The bytes/words are programmed one bytes/words at a time using the
EPROM programming mechanism of hot electron injection.