16 BIT. MBM29SL800TD Datasheet

MBM29SL800TD BIT. Datasheet pdf. Equivalent

Part MBM29SL800TD
Description (MBM29SL800TD/BD) FLASH MEMORY CMOS 8 M (1 M X 8/512 K X 16) BIT
Feature www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20871-5E FLASH MEMORY CMOS 8 M (1 M × .
Manufacture Fujitsu Media Devices
Datasheet
Download MBM29SL800TD Datasheet



MBM29SL800TD
www.DataSheet4U.com
FUJITSU SEMICONDUCTOR
DATA SHEET
FLASH MEMORY
CMOS
8 M (1 M × 8/512 K × 16) BIT
MBM29SL800TD/BD-10/12
DS05-20871-5E
s DESCRIPTION
The MBM29SL800TD/BD are a 8 M-bit, 1.8 V-only Flash memory organized as 1 Mbytes of 8 bits each or 512
Kwords of 16 bits each. The MBM29SL800TD/BD are offered in a 48-pin TSOP (I) , 48-ball FBGA and 48-ball
SCSP packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC
supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be repro-
grammed in standard EPROM programmers.
s PRODUCT LINE UP
(Continued)
Part No.
Ordering Part No.
VCC = +2.0 V ± 0.2
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
MBM29SL800TD/MBM29SL800BD
10 12
100 120
100 120
35 50
s PACKAGES
48-pin Plastic TSOP (I) 48-pin Plastic TSOP (I)
Marking Side
48-pin Plastic FBGA
48-pin Plastic SCSP
(FPT-48P-M19)
Marking Side
(FPT-48P-M20)
(BGA-48P-M12)
(WLP-48P-M03)



MBM29SL800TD
MBM29SL800TD-10/12/MBM29SL800BD-10/12
(Continued)
The standard MBM29SL800TD/BD offer access times 100 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE) ,
write enable (WE) , and output enable (OE) controls.
The MBM29SL800TD/BD are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29SL800TD/BD are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
A sector is typically erased and verified in 1.5 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29SL800TD/BD are erased when shipped from the
factory.
The devices feature single 1.8 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29SL800TD/BD memories electrically erase the entire
chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM programming mechanism of hot electron injection.
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