56F8036

www.DataSheet4U.com 56F8036 Data Sheet Preliminary Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8036 Rev. 3 01/2007 freescale.com Document Revision History Version History Rev. 0 Rev. 1 Initial public release. In Table 10-4, added an entry for flash data retention with less than 100 program/erase cycles (minimum 20 years). In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz. In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode from 400kHz to 200kHz. Changed input propagation delay values in Table 10-21 as follows: Old values: 1 μs typical, 2 μs maximum New values: 35 ns typical, 45 ns maximum Rev. 2 Rev. 3 In Table 10-20, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz. Added the following note to the description of the TMS signal in Table 2-3: Note: Always tie the TMS pin to VDD through a 2.2K resistor. Description of Change Please see http://www.freescale.com for the most current Data Sheet revision. 56F8036 Data Sheet, Rev. 3 2 Freescale Semiconductor Preliminary 56F8036 General Description Up to 32 MIPS at 32MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture 64KB (32K x 16) Program Flash 8KB (4K x 16) Unified Data/Program RAM One 6-channel PWM module clocked at up to 96MHz Two independent 5-channel 12-bit high-speed Analog-to-Digital Converters (ADCs) Two internal 12-bit Digital-to-Analog Converters (DACs) T...