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56F8367/56F8167
Data Sheet Preliminary Technical Data
56F8300 16-bit Digital Signal Controllers
MC56F8367 Rev. 8 01/2007
freescale.com
Document Revision History
Version History Rev 0 Rev 1.0 Rev 2.0 Description of Change Pre-release, Alpha customers only Initial Public Release Added output voltage maximum value and note to clarify in Table 10-1.; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering. Clarified value and unit measure for Maximum allowed PD in Table 10-3. Corrected note about average value for Flash Data Retention in Table 10-4. Added new RoHS-compliant orderable part numbers in Table 13-1. Added 160MAPBGA information, TA equation updated in Table 10-4 and additional minor edits throughout data sheet Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) and corrected Flash Endurance to 10,000 in Table 10-4. Added RoHS-compliance and “pb-free” language to back cover. Correcting MBGA pin assignments in Table 2-2 for MOSI0 and MISO0 Added information/corrected state during reset in Table 2-2. Clarified external reference crystal frequency for PLL in Table 10-14 by increasing maximum value to 8.4MHz. Corrected CLKO and HOME1 labels in Figure 11-2 and Table 11-2; replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2. • Added the following note to the description of the TMS signal in Table 2-2: Note: Always tie the TMS pin to VDD through a 2.2K resistor. • Added the following note to the description of the TRST signal in Table 2-2: Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor.
Rev 3.0 Rev 4.0
Rev 5.0 Rev 6.0 Rev 7.0 Rev. 8
Please see http://www.freescale.com for the most current data sheet revision.
56F8367 Technical Data, Rev. 8 2 Freescale Semiconductor Preliminary
56F8367/56F8167 General Description
Note: Features in italics are NOT available in the 56F8167 device.
• Up to 60 MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Access up to 4MB of off-chip program and 32MB of data memory • Chip Select Logic for glueless interface to ROM and SRAM • 512KB of Program Flash • 4KB of Program RAM • 32KB of Data Flash • 32KB of Data RAM • 32KB Boot Flash • Up to two 6-channel PWM modules • Four 4-channel, 12-bit ADCs
RSTO EMI_MODE EXTBOOT 5 VPP 2 VCAP 4 OCR_DIS VDD VSS 7 6 Digital Reg VDDA 2 Analog Reg VSSA * Configuration shown for on-chip 2.5V regulator
• Temperature Sensor • Up to two Quadrature Decoders • Optional on-chip regulator • Up to two FlexCAN modules • Two Serial Communication Interfaces (SCIs) • Up to two Serial Peripheral Interfaces (SPIs) • Up to four general-purpose Quad Timers • Computer Operating Properly (COP) / Watchdog • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 76 GPIO lines • 160-pin LQFP Package and 160 MAPBGA
RESET 6 3 4 6 3 4 4 4 5 4 4 PWM Outputs Current Sense Inputs or GPIOC Fault Inputs PWM Outputs Current Sense Inputs or GPIOD Fault Inputs AD0 AD1 VREF AD0 AD1
PWMA
JTAG/ EOnCE Port
16-Bit 56800E Core
Low Voltage Supervisor
Bit Manipulation Unit
PWMB
Program Controller and Hardware Looping Unit
Address Generation Unit
Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators
ADCA
PAB PDB CDBR CDBW
Memory
ADCB
Program Memory 256K x 16 Flash 2K x 16 RAM Boot ROM 16K x 16 Flash
R/W Control XDB2 XAB1 XAB2
External Address Bus Switch
6 2 8 4 3
External Data Bus Switch
A0-5 or GPIOA8-13 A6-7 or GPIOE2-3 A8-15 or GPIOA0-7 GPIOB0-3 (A16-19) GPIOB4 (A20, prescaler_clock) GPIOB5-7 (A21-23, clk0-3**) D0-6 or GPIOF9-15 D7-15 or GPIOF0-8 WR RD GPIOD2-5 or CS4 -7 PS / CS0 (GPIOD8) DS / CS1 (GPIOD9) GPIOD0 (CS2 or CAN2_TX) GPIOD1 (CS3 or CAN2_RX)
Temp_Sense Quadrature Decoder 0 or Quad Timer A or GPIOC Quadrature Decoder 1 or Quad Timer B or SPI1 or GPIOC Quad Timer C or GPIOE Quad Timer D or GPIOE FlexCAN
4
Data Memory
16K x 16 Flash 16K x 16 Flash
PDB CDBR CDBW
External Bus Interface Unit
PAB
System Bus Control
7 9
4
IPBus Bridge (IPBB)
Decoding Peripherals
Clock resets
Bus Control
4
2
Peripheral Device Selects
RW Control
IPAB
IPWDB
IPRDB
GPIO or EMI CS or FlexCAN2
4 2
PLL
SPI0 or GPIOE 4
SCI1 or GPIOD 2
SCI0 or GPIOE 2
COP/ Watchdog
Interrupt Controller IRQA IRQB
System O Integration R Module CLKO
P
O Clock Generator S C
XTAL EXTAL **See Table 2-2 for explanation
CLKMODE
56F8367/56F8167 Block Diagram
56F8367 Technical Data, Rev. 8 Freescale Semiconductor Preliminary 3
Table of Contents
Part 1: Overview. . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8367/56F8167 Features . . . . . . . . . . . . . 5 Device Description . . . . . . . . . . . . . . . . . . . . 7 Awa.