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74LVC594A
8-bit shift register with output register
Rev. 01 — 24 May 2007 Product data sheet
1. General description
The 74LVC594A is an 8-bit serial-in/serial or parallel-out shift register with a storage register. Separate clock and reset inputs are provided on both shift and storage registers. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The shift register has a serial input (DS) and a serial output (Q7S) for cascading purposes. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. A LOW level on one of the two register reset pins (SHR and STR) will clear the corresponding register.
2. Features
s s s s s s s s 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Balanced propagation delays All inputs have Schmitt-trigger action Complies with JEDEC standard JESD8-B/JESD36 ESD protection: x HBM JESD22-A114-D exceeds 2000 V x CDM JESD22-C101-C exceeds 1000 V s Specified from −40 °C to +85 °C and −40 °C to +125 °C.
3. Applications
s Serial-to-parallel data conversion s Remote control holding register
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NXP Semiconductors
74LVC594A
8-bit shift register with output register
4. Ordering information
Table 1. Ordering information Package Temperature range 74LVC594AD 74LVC594APW 74LVC594ABQ −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name SO16 TSSOP16 DHVQFN16 Description plastic small outline package; 16 leads; body width 3.9 mm Version SOT109-1 Type number
plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1
5. Functional diagram
SHCP STCP 11 12 9 15 1 2 DS 14 3 4 5 6 7 10 SHR 13 STR
mbc319
Q7S DS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 STR STCP SHCP SHR
14 11 10 9 12 13 8-BIT STORAGE REGISTER Q7S 8-STAGE SHIFT REGISTER
15 1
2
3
4
5
6
7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
mbc320
Fig 1. Logic symbol
Fig 2. Functional diagram
74LVC594A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 24 May 2007
2 of 19
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NXP Semiconductors
74LVC594A
8-bit shift register with output register
STAGE 0 DS D Q D
STAGES 1 TO 6 Q
STAGE 7 D Q Q7S
FFSH0 CP R SHCP
FFSH7 CP R
SHR
D
Q
D CP
Q
FFST0 CP R STCP
FFST7 R
STR
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
mbc321
Fig 3. Logic diagram
SHCP
DS STCP
SHR STR Q0
Q1
Q6
Q7
Q7S
mbc323
Fig 4. Timing diagram
74LVC594A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 24 May 2007
3 of 19
www.DataSheet4U.com
NXP Semiconductors
74LVC594A
8-bit shift register with output register
6. Pinning information
6.1 Pinning
74LVC594A
terminal 1 index area 16 VCC 15 Q0 14 DS 13 STR 12 STCP 11 SHCP 10 SHR 8 GND Q7S 9 Q1 2 3 4 5 6 7 1 Q2 16 VCC 15 Q0 14 DS 13 STR 12 STCP 11 SHCP 10 SHR 9
001aag287
74LVC594A
Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND 1 2 3 4 5 6 7 8
Q3 Q4 Q5 Q6 Q7
Q7S
001aag288
Transparent top view
Fig 5. Pin configuration SO16 and TSSOP16
Fig 6. Pin configuration DHVQFN16
6.2 Pin description
Table 2. Symbol Q[0:7] GND Q7S SHR SHCP STCP STR DS VCC Pin description Pin 8 9 10 11 12 13 14 16 Description ground (0 V) serial data output shift register reset (active LOW) shift register clock input storage register clock input storage register reset (active LOW) serial data input supply voltage 15, 1, 2, 3, 4, 5, 6, 7 parallel data output
74LVC594A_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 24 May 2007
4 of 19
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NXP Semiconductors
74LVC594A
8-bit shift register with output register
7. Functional description
Table 3. Input SHCP STCP SHR X X X ↑ X X ↑ X L X L H STR X L H X DS X X X H Function table[1] Output Q7S L NC L Q6S Qn NC L L NC a LOW-state on SHR only affects the shift register a LOW-state on STR only affects the storage register empty shift register loaded into storage register logic HIGH level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stage.