LP62S4096E-T

LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 512K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 2.0 History Change VCCmax from 3.3V to 3.6V Add product family and 55ns specification Issue Date January 25, 2002 Remark (January, 2002, Version 2.0) AMIC Technology, Inc. LP62S4096E-T Series 512K X 8 BIT LOW VOLTAGE CMOS SRAM Features n Power supply range: 2.7V to 3.6V n Access times: 55ns / 70ns (max.) n Current: Very low power version: Operating: 30mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 2V (min.) n Available in 32-pin TSOP/TSSOP 36-ball CSP package General Description The LP62S4096E-T is a low operating current 4,194,304-bit static random access memory organized as 524,288 words by 8 bits and operates on a low power supply range: 2.7V to 3.3V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. n CE2 pin for CSP package only Power Dissipation Data Retention Standby Operating (ICCDR, Typ.) (ISB1, Typ.) (ICC2, Typ.) 0.08µA 0.3µA 5mA Product Family Product Famil...