SGRAM. MSM54V24632A Datasheet

MSM54V24632A SGRAM. Datasheet pdf. Equivalent

Part MSM54V24632A
Description SGRAM
Feature Pr www.DataSheet4U.com ¡ Semiconductor y ar in im el ¡ Semiconductor MSM54V24632A 131,072-Word ¥ .
Manufacture OKI electronic
Datasheet
Download MSM54V24632A Datasheet




MSM54V24632A
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MSM54V24632A
11 Feb. 1998
MSM54V24632A
131,072-Word ¥ 32-Bit ¥ 2-Bank SGRAM without Graphics Functions
DESCRIPTION
The MSM54V24632A is a synchronous graphics random access memory without graphics
oriented functions; Block Write, Write per bit, Single write and Burst stop. It is organized as 128K
words ¥ 32 bits ¥ 2 banks.
This device can operate up to 125MHz by using synchronous interface.
FEATURES
• 131,072-words ¥ 32 bits ¥ 2 banks memory
• Single 3.3 V±0.3 V power supply
• LVTTL compatible inputs and outputs
• All input signals are latched at rising edge of system clock
• Auto precharge and controlled precharge
• Internal pipelined operation: column address can be changed every clock cycle
• Dual internal banks controlled by A9 (Bank Address: BA)
• Independent byte operation via DQM0 to DQM3
• Simplified function (No Block write, Write per bit, Single write and Burst stop)
• Programmable burst sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable CAS latency (1, 2 and 3)
• Power Down operation and Clock Suspend operation
• Auto refresh and Self refresh capability
• 1,024 refresh cycle / 16 ms
• Package :
100-pin plastic QFP (QFP100-P-1420-0.65-BK4) (Product : MSM54V24632A-xxGS-BK4)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM54V24632A-8
MSM54V24632A-10
MSM54V24632A-12
Clock Frequency
MHz (Max.)
125
100
83
Package
100-pin Plastic QFP (14 ¥ 20 mm)
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MSM54V24632A
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MSM54V24632A
PIN CONFIGURATION (TOP VIEW)
100pin Plastic QFP
DQ3 1
Vcc(Q) 2
DQ4 3
DQ5 4
Vss(Q) 5
DQ6 6
DQ7 7
Vcc(Q) 8
DQ16 9
DQ17 10
Vss(Q) 11
DQ18 12
DQ19 13
Vcc(Q) 14
Vcc 15
Vss 16
DQ20 17
DQ21 18
Vss(Q) 19
DQ22 20
DQ23 21
Vcc(Q) 22
DQM0 23
DQM2 24
WE 25
CAS 26
RAS 27
CS 28
A9 29
NC 30
¡ Semiconductor
80 DQ28
79 Vcc(Q)
78 DQ27
77 DQ26
76 Vss(Q)
75 DQ25
74 DQ24
73 Vcc(Q)
72 DQ15
71 DQ14
70 Vss(Q)
69 DQ13
68 DQ12
67 Vcc(Q)
66 Vss
65 Vcc
64 DQ11
63 DQ10
62 Vss(Q)
61 DQ9
60 DQ8
59 Vcc(Q)
58 NC
57 DQM3
56 DQM1
55 CLK
54 CKE
53 NC
52 NC
51 A8
Pin Name
CLK
CS
CKE
A0 - A8
A9
RAS
CAS
WE
Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Pin Name
Function
DQM0~DQM3 Data Input/Output Mask
DQi Data Input/Output
VCC
VSS
VCC(Q)
VSS(Q)
NC
Power Supply (3.3 V)
Ground (0 V)
Data Output Power Supply (3.3 V)
Data Output Ground (0 V)
No Connection
Note: The same power supply voltage must be provided to every VCC pin and VCC(Q)pin.
The same GND voltage level must be provided to every VSS pin and VSS(Q) pin.
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