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XR16V2552 Dataheets PDF



Part Number XR16V2552
Manufacturers Exar Corporation
Logo Exar Corporation
Description HIGH PERFORMANCE DUART
Datasheet XR16V2552 DatasheetXR16V2552 Datasheet (PDF)

www.DataSheet4U.com JUNE 2006 PRELIMINARY XR16V2552 REV. P1.0.0 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO GENERAL DESCRIPTION The XR16V25521 (V2552) is a high performance dual universal asynchronous receiver and transmitter (UART) with 16 byte TX and RX FIFOs. The device operates from 2.25 to 3.6 volts with 5 Volt tolerant inputs and is pin-to-pin compatible to Exar’s ST16C2552 and XR16L2552. The V2552 register set is compatible to the ST16C2552 and the XR16L2552. It supports the Exar’s enhan.

  XR16V2552   XR16V2552



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www.DataSheet4U.com JUNE 2006 PRELIMINARY XR16V2552 REV. P1.0.0 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO GENERAL DESCRIPTION The XR16V25521 (V2552) is a high performance dual universal asynchronous receiver and transmitter (UART) with 16 byte TX and RX FIFOs. The device operates from 2.25 to 3.6 volts with 5 Volt tolerant inputs and is pin-to-pin compatible to Exar’s ST16C2552 and XR16L2552. The V2552 register set is compatible to the ST16C2552 and the XR16L2552. It supports the Exar’s enhanced features of selectable FIFO trigger level, automatic hardware (RTS/CTS) and software (Xon/Xoff) flow control, and a complete modem interface. Onboard registers provide the user with operational status and data error flags. An internal loopback capability allows system diagnostics. Independent programmable baud rate generators are provided in each channel to select data rates up to 16 Mbps at 3.3 Volt with 4X sampling clock. The V2552 is available in 44-pin PLCC and 32-pin QFN packages. NOTE: 1 Covered by U.S. Patent #5,649,122 FEATURES • 2.25 to 3.6 Volt Operation • 5 Volt Tolerant Inputs • Pin-to-pin compatible to Exar’s XR16L2552 in the 44-PLCC package • Two independent UART channels ■ ■ Register set identical to 16V2550 Data rate of up to 16 Mbps at 3.3 V, and 12.5 Mbps at 2.5 V with 4X sampling rate Fractional Baud Rate Generator Transmit and Receive FIFOs of 16 bytes Selectable TX and RX FIFO Trigger Levels Automatic Hardware (RTS/CTS) Flow Control Automatic Software (Xon/Xoff) Flow Control Wireless Infrared (IrDA 1.0) Encoder/Decoder Automatic sleep mode Full modem interface ■ ■ ■ ■ ■ ■ ■ ■ APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls FIGURE 1. XR16V2552 BLOCK DIAGRAM • Alternate Function Register • Device Identification and Revision • Crystal oscillator (up to 32MHz) or external clock (up to 64MHz) input • 44-PLCC and 32-QFN packages * 5 Volt Tolerant Inputs A2:A0 D7:D0 IOR# IOW# CS# CHSEL INTA INTB TXRDYA# TXRDYB# RXRDYA# RXRDYB# Reset UART Channel A UART Regs 8-bit Data Bus Interface BRG 16 Byte TX FIFO TX & RX IR ENDEC 2.25 to 3.6 Volt VCC GND TXA, RXA, DTRA#, DSRA#, RTSA#, DTSA#, CDA#, RIA#, OP2A# 16 Byte RX FIFO TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB#, OP2B# XTAL1 XTAL2 UART Channel B (same as Channel A) Crystal Osc/Buffer Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XR16V2552 PRELIMINARY REV. P1.0.0 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO FIGURE 2. PIN OUT ASSIGNMENT TXRDYA# DSRA# 41 44 43 RIA# D4 D3 D2 D1 D0 42 D5 D6 D7 A0 7 8 9 10 40 6 5 4 3 2 1 CTSA# CDA# VCC 39 38 37 36 35 RXA TXA DTRA# RTSA# MFA# INTA VCC TXRDYB# RIB# XTAL1 11 GND 12 XTAL2 13 A1 14 XR16V2552 44-pin PLCC 34 33 32 31 A2 15 CHSEL 16 INTB 17 CS# 18 MFB# 19 IOW# 20 RESET 21 GND 22 RTSB# 23 IOR# 24 RXB 25 TXB 26 DTRB# 27 CTSB# 28 30 CDB# 29 DSRB# 31 D4 30 D3 29 D2 D1 32 D5 28 27 D0 26 25 24 RXA 23 TXA 22 RTSA# 21 INTA 20 GND 19 NC 18 NC 17 CTSB# TXB 16 D6 D7 A0 XTAL1 XTAL2 A1 A2 CHSEL 1 2 3 4 5 6 7 8 RTSB# 13 IOW# 11 RESET 12 IOR# 14 RXB 15 CS# 10 9 XR16V2552 32-pin QFN ORDERING INFORMATION PART NUMBER XR16V2552IL32 XR16V2552IJ PACKAGE 32-pin QFN 44-Lead PLCC OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C DEVICE STATUS Active Active INTB 2 CTSA# VCC PRELIMINARY REV. P1.0.0 XR16V2552 HIGH PERFORMANCE DUART WITH 16-BYTE FIFO PIN DESCRIPTIONS Pin Description NAME 32-QFN PIN # 44-PLCC PIN # TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 IOR# 7 6 3 2 1 32 31 30 29 28 27 14 15 14 10 9 8 7 6 5 4 3 2 24 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional). I/O I Input/Output Read Strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. Input/Output Write Strobe (active low). The falling edge instigates an internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. UART chip select (active low). This function selects channel A or B in accordance with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the V2552. Channel Select - UART channel A or B is selected by the logical state of this pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A. Normally, CHSEL could just be an address line from the user CPU such as A4. Bit-0 of the Alternate Function Register (AFR) can temporarily override CHSEL function, allowing the user to write to both channe.


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