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XRT73L03B Dataheets PDF



Part Number XRT73L03B
Manufacturers Exar Corporation
Logo Exar Corporation
Description 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
Datasheet XRT73L03B DatasheetXRT73L03B Datasheet (PDF)

www.DataSheet4U.com XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 OCTOBER 2003 GENERAL DESCRIPTION The XRT73L03B, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications. Each channel of the XRT73L03B can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) r.

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www.DataSheet4U.com XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 OCTOBER 2003 GENERAL DESCRIPTION The XRT73L03B, 3-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications. Each channel of the XRT73L03B can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. Each channel can be configured to operate in a mode/data rate that is independent of the other channels. In the transmit direction, each channel encodes input data to either B3ZS (DS3/STS-1) or HDB3 (E3) format and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer. In the receive direction, the XRT73L03B performs equalization on incoming signals, performs Clock Recovery, decodes data from either B3ZS or HDB3 format, converts the receive data into TTL/CMOS format, checks for LOS or LOL conditions and detects and declares the occurrence of Line Code Violations. FEATURES • Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L03A • Meets E3/DS3/STS-1 Jitter Tolerance Requirements • Contains a 4-Wire Microprocessor Serial Interface • Full Loop-Back Capability • Transmit and Receive Power Down Modes • Full Redundancy Support • Uses Minimum External components • Single +3.3V Power Supply • Low power CMOS design • 5V tolerant I/O • -40°C to +85°C Operating Temperature Range • Available in a 120 pin LQFP package APPLICATIONS • Digital Cross Connect Systems • CSU/DSU Equipment • Routers • Fiber Optic Terminals • Multiplexers • ATM Switches FIGURE 1. XRT73L03B BLOCK DIAGRAM E3_(n) STS-1/DS3_(n) Host/(HW) RLOL_(n) EXClk_(n) RxOFF RxClkINV RTIP_(n) RRing_(n) REQEN_(n) AGC/ Equalizer Peak Detector Slicer Clock Recovery Data Recovery Invert RxClk_(n) LOSTHR_(n) SDI SDO SClk CS REGR Serial Processor Interface LOS Detector HDB3/ B3ZS Decoder RPOS_(n) RNEG_(n) LCV_(n) ENDECDIS RLOS_(n) LLB_(n) RLB_(n) TAOS_(n) Loop MUX TTIP_(n) Pulse Shaping TRing_(n) MTIP_(n) MRing_(n) DMO_(n) Tx Control HDB3/ B3ZS Encoder Transmit Logic Duty Cycle Adjust TPData_(n) TNData_(n) TxClk_(n) TxLEV_(n) TxOFF_(n) Device Monitor Channel 0 - (n) = 0 Channel 1 - (n) = 1 Channel 2 - (n) = 2 Notes: 1. (n) = 0, 1, or 2 for respective Channels 2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode. Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 TYPICAL APPLICATIONS FIGURE 2. MULTICHANNEL ATM APPLICATION RPOS RNEG RxClk RPOS RNEG RxClk RPOS RNEG RxLineClk RRPOS RRNEG RRClk RTIP RRing ATM Switch/ SAR XRT74L73 XRT71D03 MClk XRT73L03B TPOS TNEG TxClk TPOS TNEG TxLineClk TTIP TRing 3 Channel E3/DS3 ATM UNI 3 Channel E3/DS3 J/A 3 Channel E3/DS3 LIU FIGURE 3. MULTISERVICE - FRAME RELAY APPLICATION RPOS RNEG RxLineClk RRPOS RRNEG RRClk RPOS RNEG RxClk RPOS RNEG RxClk RTIP RRing Frame Relay XRT72L56 XRT71D03 MClk XRT73L03B TPOS TNEG TxLineClk TPOS TNEG TxClk TTIP TRing 6 Channel E3/DS3 Framer 2 x 3 Channel E3/DS3 J/A 2 x 3 Channel E3/DS3 LIU TRANSMIT INTERFACE CHARACTERISTICS: • Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal from the line • Integrated Pulse Shaping Circuit • Built-in B3ZS/HDB3 Encoder (which can be disabled) • Contains Transmit Clock Duty Cycle Correction Circuit on-chip • Generates pulses that comply with the ITU-T G.703 pulse template (E3 applications) • Generates pulses that comply with the DSX-3 pulse template as specified in Bellcore GR-499-CORE and ANSI T1.102_1993 • Generates pulses that comply with the STSX-1 pulse template as specified in Bellcore GR-253CORE • Transmitter can be turned off in order to support redundancy designs RECEIVE INTERFACE CHARACTERISTICS: • Integrated Adaptive Receive Equalization (optional) and Timing Recovery • Declares and Clears the LOS defect per ITU-T G.775 requirements (E3 and DS3 applications) • Meets Jitter Tolerance Requirements as specified in ITU-T G.823_1993 (E3 Applications) • Meets Jitter Tolerance Requirements as specified in Bellcore GR-499-CORE (DS3 Applications) • Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms • Built-in B3ZS/HDB3 Decoder (which can be disabled) • Recovered Data can be muted while the LOS Condition is declared • Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment • Receiver can be powered down in order to conserve power in redundancy designs 2 XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT REV. 1.0.1 FIGURE 4. PIN OUT OF THE XRT73L03B IN THE 120 PIN LQFP PACKAGE REGR/(RxClkINV) STS-1/DS3_1 AGND_2 SR/(DR) E3_1 NC NC LOSTHR_1 LLB_1 RLB_1 RxAVDD_1 RRing_1 RTIP.


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