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XRD9825
16-Bit Linear CIS/CCD Sensor Signal Processor with Serial Control
May 2000-3
FEATURES
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16-Bit Resolution One-channel 12MSPS Pixel Rate Triple-channel 4MSPS Pixel Rate 6-Bit Programmable Gain Amplifier 8-Bit Programmable Offset Adjustment CIS or CCD Compatibility Internal Clamp for CIS or CCD AC Coupled Configurations No Missing Codes at 10MHz ADC Clock 3.3V or 5V Operation & I/O Compatibility Serial Load Control Registers
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Low Power CMOS: 200mW-typ Low Cost 20-Lead Packages USB Compliant
APPLICATIONS
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Color and Grayscale Flatbed Scanners Color and Grayscale Sheetfed Scanners Multifunction Peripherals Digital Color Copiers General Purpose CIS or CCD Imaging Low Cost Data Acquisition Simple and Direct Interface to Canon 600 DPI Sensors
GENERAL DESCRIPTION The XRD9825 is a complete linear CIS or CCD sensor signal processor on a single monolithic chip. The XRD9825 includes a high speed 16-bit resolution ADC, a 6-bit Programmable Gain Amplifier with gain adjustment of 1 to 10, and 8-bit programmable input referred offset calibration range of 800mV. In the CCD configuration the input signal is AC coupled with an external capacitor. An internal clamp sets the black level. In the CIS configuration, the clamp switch can be disabled and the CIS output signal is DC coupled from the CIS sensor to the XRD9825. The CIS signal is level shifted to VRB in order to use the full range of the ADC. In the CIS configuration the input can also be AC coupled similar to the CCD configuration. This enables CIS signals with large black levels to be internally clamped to a DC reference equal to the black level. The DC reference is internally subtracted from the input signal. The CIS configuration can also be used in other applications that do not require CDS function, such as low cost data acquisition.
ORDERING INFORMATION
Package Type 20-Lead SOIC 20-Lead SSOP
Temperature Range 0°C to +70°C 0°C to +70°C
Part Number XRD9825ACD XRD9825ACU
Rev. 1.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRD9825
* CIS REF Circuit
VBG
AVDD
RED CLAMP
* CIS REF Circuit Triple S/H & 3-1 MUX
Power Down DVDD + BUFFER _ PGA VRT RL16-BIT ADC 16 DATA I/O PORT 8 DB7:0 VREF+
GRN
BLU DC Reference VDCEXT INT/EXT_V DCREF CLP 6-BIT GAIN REGISTERS DC/AC R G B 6 G<5:0> V DCREF VRB
DGND
Power Down
AVDD AGND
8-BIT DAC AGND 8 CIS/CCD 8-BIT OFFSET REGISTERS VRT CIS CCD R G B O<7:0>
AGND SYNCH CLAMP TIMING & CONTROL LOGIC ADCCLK
Note: * For Canon CIS Sensor
Figure 1. Functional Block Diagram
Rev. 1.00
2
XRD9825
PIN CONFIGURATION
DVDD 1 DB0 DB1 DB2 DB3 DB4 DB5/SCLK DB6/SDATA DB7/LD
2 3 4 5
20 AVDD 19 RED 18 GRN 17 BLU 16 VDCEXT
XRD9825ACD
6 7 8 9 15 VREF+ 14 AGND 13 SYNCH 12 CLAMP 11 ADCCLK
DGND 10
20-Lead SOIC
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol DVDD DB0 DB1 DB2 DB3 DB4 DB5/SCLK DB6/SDATA DB7/LD DGND ADCCLK CLAMP SYNCH AGND VREF+ VDCEXT BLU GRN RED AVDD Description Digital VDD (for Output Drivers) Data Output Bit 0 Data Output Bit 1 Data Output Bit 2 Data Output Bit 3 Data Output Bit 4 Data Output Bit 5 & Data Input SCLK Data Output Bit 6 & Data Input SDATA Data Output Bit 7 & LD Digital Ground (for Output Drivers) A/D Converter Clock Clamp and Video Sample Clock Start of New Line and Serial Data Input Control Analog Ground A/D Positive Reference for Decoupling Cap External DC Reference Blue Input Green Input Red Input Analog Power Supply
Rev. 1.00
3
XRD9825
ELECTRICAL CHARACTERISTICS Test Conditions: AVDD=DVDD=5V, ADCCLK=12MHz, 50% Duty Cycle, TA=25°C unless otherwise specified.
Symbol Parameter Min. Typ. Max. Unit Conditions
Power Supplies AVDD DVDD IDD IDDPD RES Fs DNL VRB ∆VREF RL PGARES PGAGMIN PGAGMAX PGAGD VBLACK DACRES OFFMIN OFFMAX OFFMIN OFFMAX OFF∆ Analog Power Supply Digital I/O Power Supply Supply Current Power Down Power Supply Current Resolution Maximum Sampling Rate Differential Non-Linearity Bottom Reference Voltage Differential Reference Voltage (VRT - VRB) Ladder Resistance 300 600 780 Ω PGA & Offset DAC Specifications PGA Resolution Minimum Gain Maximum Gain Gain Adjustment Step Size Black Level Input Range Offset DAC Resolution Minimum Offset Adjustment Maximum Offset Adjustment Minimum Offset Adjustment Maximum Offset Adjustment Offset Adjustment Step Size -100 8 -250 +500 -450 +350 -200 +600 -400 +400 3.125 -150 +700 -350 +450 6 0.950 9.5 1.0 10.0 0.14 500 1.050 10.50 Bits V/V V/V V/V mV Bits mV mV mV mV mV Mode 111, D5=0 (Note 1) Mode 111, D5=0 Mode 111, D5=1 (Note 1) Mode 111, D5=1 DC Configuration 0.3 16 12 -0.7, +1.5 -0.8, +2.0 AVDD/10 0.67AV DD V V 3.0 3.0 25 3.3 3.3 40 5.5 5.5 60 50 V V mA µA Bits MSPS LSB ADCCLK = 10MHz ADCCLK = 12MHz (Note 2) DVDD < AVDD VDD=5V VDD=5V
ADC Specifications
Note 1: Note 2:
The additional ±100 mV of adjustment with respect to the black level input range is needed to compensate for any additional off.