XRK69773

www.DataSheet4U.com APRIL 2006 PRELIMINARY XRK69773 REV. P1.0.0 1:12 LVCMOS PLL CLOCK GENERATOR GENERAL DESCRIPTION The XRK69773 is a PLL based LVCMOS Clock Generator targeted for high performance and low skew clock distribution applications. The XRK69773 can select between one of three reference inputs and provides 14 LVCMOS outputs -12 outputs (3 banks of 4) for clock distribution, 1 for feedback and 1 for synchronization. The XRK69773 is a highly flexible device. It has 3 selectable inputs, (one differential and two single-ended inputs) to support system clock redundancy. Up to three different clock frequencys can be generated and outputted on the three output banks. Switching the internal reference clock is controlled by the control input, CLK_SEL. The XRK69773 uses PLL technology to frequency lock its outputs to the input reference clock. The divider in the feedback path will determine the frequency of the VCO. Each of the separate output banks can individually divide down the VCO output frequency. This allows the XRK69773 to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. The outputs of the XRK69773 can individually be immobilized, in the low state, by use of the clock stop feature. All outputs except QC0 and QFB can be immobilized through a 2 pin serial interface. Global output disabling and reset can be achieved the control input MR/OE. The XRK69773 also has a QSYNC output which can be used for system synchronization p...