XRK799J93

www.DataSheet4U.com xr DECEMBER 2006 XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER REV. 1.0.1 GENERAL DESCRIPTION The XRK799J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance. The XRK799J93 Intelligent Dynamic Clock Switch circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will FIGURE 1. BLOCK DIAGRAM OF THE XRK799J93 CLK _Selected INP1Bad INP0Bad Man_Override Alarm_Reset Sel_CLK be latched (H). If that CLK is the primary clock, the device will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. FEATURES Fully Integrated PLL Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32-Lead TQFP Packaging Dynamic Switch Logic Qb0 Qb0 Qb1 Qb1 ÷2 Qb2 Qb2 Qa0 Qa0 Qa1 Qa1 CLK0 CLK0 CLK1 CLK1 Ext_FB Ext_FB PLL_En MR PLL 160-380MHz ÷4 Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 w...