Card IC. DS3100 Datasheet

DS3100 IC. Datasheet pdf. Equivalent


Maxim Integrated Products DS3100
www.DataSheet4U.com
www.maxim-ic.com
GENERAL DESCRIPTION
When paired with an external TCXO or OCXO, the
DS3100 is a complete central timing and
synchronization solution for SONET/SDH network
elements. With two multiprotocol BITS/SSU receivers
and 14 input clocks, the device directly accepts both
external timing and line timing from a large number of
line cards. All input clocks are continuously monitored
for frequency accuracy and activity. Any two of the input
clocks can be selected as the references for the two
core DPLLs. The T0 DPLL complies with the Stratum 3
and 3E requirements of GR1244, GR-253, and the
requirements of G.812 Type III and G.813. From the
output of the core DPLLs, a wide variety of output clock
frequencies and frame pulses can be produced
simultaneously on the 11 output clock pins. Two
DS3100 devices can be configured in a master/slave
arrangement for timing card equipment protection.
The DS3100 registers and I/O pins are backward
compatible with Semtech’s ACS8520 and ACS8530
timing card ICs.
APPLICATIONS
SONET/SDH ADMs, MSPPs, and MSSPs
Digital Cross-Connects
DSLAMs
Service Provider Routers
FUNCTIONAL DIAGRAM
TIMING FROM
LINE CARDS
(VARIOUS RATES) 14
TIMING FROM
BITS/SSU
(DS1, E1, CC, ETC.) 2
LOCAL TCXO
OR OCXO
DS3100 2
SONET/SDH
SYNCHRONIZATION
IC
11
TIMING TO BITS/SSU
(DS1, E1, CC, ETC.)
TIMING TO
LINE CARDS
(VARIOUS RATES)
CONTROL STATUS
DS3100
Stratum 3/3E Timing Card IC
FEATURES
Synchronization Subsystem for Stratum 3E, 3,
4E and 4, SMC and SEC
- Meets Requirements of GR-1244 Stratum 3/3E,
GR-253, G.812 Types I, III and IV, and G.813
- Stratum 3E Holdover Accuracy with Suitable
External Oscillator
- Programmable Bandwidth, 0.5mHz to 70Hz
- Hitless Reference Switching on Loss of Input
- Phase Build-Out and Transient Absorption
- Locks to and Generates 125MHz for Gigabit
Synchronous Ethernet per ITU-T G.8261
14 Input Clocks
- 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any
Multiple of 8kHz Up to 125MHz
- Two LVDS/LVPECL/CMOS/TTL Inputs Accept
Nx8kHz Up to 125MHz Plus 155.52MHz
- Two 64kHz Composite Clock Receivers
- Continuous Input Clock Quality Monitoring
- Separate 2/4/8kHz Frame Sync Input
11 Output Clocks
- Five CMOS/TTL Outputs Drive Any Internally
Produced Clock Up to 77.76MHz
- Two LVDS Outputs Each Drive Any Internally
Produced Clock Up to 311.04MHz
- One 64kHz Composite Clock Transmitter
- One 1.544MHz/2.048MHz Output Clock
- Two Sync Pulses: 8kHz and 2kHz
- Output Clock Rates Include 2kHz, 8kHz, NxDS1,
NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz,
38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz,
125MHz, 155.52MHz, 311.04MHz
Two Multiprotocol BITS/SSU Transceivers
- Receive and Transmit DS1, E1, 2048kHz, and
6312kHz Timing Signals
- Insert and Extract SSM Messages (DS1, E1)
- Automatically Invalidate Clocks on LOS, OOF,
AIS, and Other Defects
Internal Compensation for Master Clock
Oscillator Frequency Accuracy
Processor Interface: 8-Bit Parallel or SPI Serial
1.8V Operation with 3.3V I/O (5V Tolerant)
ORDERING INFORMATION
PART
TEMP RANGE
DS3100GN -40°C to +85°C
DS3100GN+ -40°C to +85°C
+Denotes a lead-free package.
PIN-PACKAGE
256 CSBGA (17mm) 2
256 CSBGA (17mm) 2
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS3100 Datasheet
Recommendation DS3100 Datasheet
Part DS3100
Description Stratum 3/3E Timing Card IC
Feature DS3100; www.DataSheet4U.com DS3100 Stratum 3/3E Timing Card IC www.maxim-ic.com GENERAL DESCRIPTION When p.
Manufacture Maxim Integrated Products
Datasheet
Download DS3100 Datasheet




Maxim Integrated Products DS3100
DS3100 Stratum 3/3E Timing Card IC
TABLE OF CONTENTS
1. STANDARDS COMPLIANCE ................................................................................................7
2. BLOCK DIAGRAM.................................................................................................................8
3. APPLICATION EXAMPLE .....................................................................................................9
4. DETAILED DESCRIPTION ..................................................................................................10
5. DETAILED FEATURES .......................................................................................................12
5.1 T0 DPLL FEATURES....................................................................................................................12
5.2 T4 DPLL FEATURES....................................................................................................................12
5.3 INPUT CLOCK FEATURES .............................................................................................................12
5.4 OUTPUT CLOCK FEATURES ..........................................................................................................13
5.5 REDUNDANCY FEATURES.............................................................................................................13
5.6 BITS TRANSCEIVER FEATURES....................................................................................................13
5.6.1 General......................................................................................................................................... 13
5.6.2 Receiver ....................................................................................................................................... 13
5.6.3 Transmitter ................................................................................................................................... 14
5.7 COMPOSITE CLOCK I/O FEATURES...............................................................................................14
5.8 GENERAL FEATURES ...................................................................................................................14
6. PIN DESCRIPTIONS............................................................................................................15
7. FUNCTIONAL DESCRIPTION .............................................................................................24
7.1 OVERVIEW ..................................................................................................................................24
7.2 DEVICE IDENTIFICATION AND PROTECTION ...................................................................................25
7.3 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION...........................................................25
7.4 INPUT CLOCK CONFIGURATION ....................................................................................................26
7.4.1 Signal Format Configuration......................................................................................................... 26
7.4.2 Frequency Configuration .............................................................................................................. 28
7.5 INPUT CLOCK QUALITY MONITORING ............................................................................................29
7.5.1 Frequency Monitoring................................................................................................................... 29
7.5.2 Activity Monitoring ........................................................................................................................ 29
7.5.3 Selected Reference Activity Monitoring ....................................................................................... 30
7.5.4 Composite Clock Inputs ............................................................................................................... 30
7.6 INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING ..................................................................31
7.6.1 Priority Configuration.................................................................................................................... 31
7.6.2 Automatic Selection Algorithm ..................................................................................................... 31
7.6.3 Forced Selection .......................................................................................................................... 32
7.6.4 Ultra-Fast Reference Switching.................................................................................................... 32
7.6.5 External Reference Switching Mode ............................................................................................ 32
7.6.6 Output Clock Phase Continuity During Reference Switching ...................................................... 33
7.7 DPLL ARCHITECTURE AND CONFIGURATION ................................................................................33
7.7.1 T0 DPLL State Machine ............................................................................................................... 33
7.7.2 T4 DPLL State Machine ............................................................................................................... 36
7.7.3 Bandwidth..................................................................................................................................... 37
7.7.4 Damping Factor............................................................................................................................ 38
7.7.5 Phase Detectors........................................................................................................................... 38
7.7.6 Loss of Phase Lock Detection...................................................................................................... 39
7.7.7 Phase Monitor and Phase Build-Out............................................................................................ 40
7.7.8 Input to Output Phase Adjustment ............................................................................................... 41
7.7.9 Phase Recalibration ..................................................................................................................... 41
7.7.10 Frequency and Phase Measurement ........................................................................................... 41
7.7.11 Input Wander and Jitter Tolerance ............................................................................................... 42
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Maxim Integrated Products DS3100
DS3100 Stratum 3/3E Timing Card IC
7.7.12 Jitter and Wander Transfer........................................................................................................... 42
7.7.13 Output Jitter and Wander ............................................................................................................. 43
7.8 OUTPUT CLOCK CONFIGURATION.................................................................................................44
7.8.1 Signal Format Configuration......................................................................................................... 45
7.8.2 Frequency Configuration .............................................................................................................. 45
7.9 EQUIPMENT REDUNDANCY CONFIGURATION.................................................................................54
7.9.1 Master-Slave Pin Feature............................................................................................................. 55
7.9.2 Master-Slave Output Clock Phase Alignment .............................................................................. 55
7.9.3 Master-Slave Frame and Multi-Frame Alignment with the SYNC2K Pin ..................................... 56
7.10 MULTIPROTOCOL BITS TRANSCEIVERS ........................................................................................58
7.10.1 Master Clock Connections ........................................................................................................... 59
7.10.2 Receiver Clock Connections ........................................................................................................ 59
7.10.3 Transmitter Clock Connections .................................................................................................... 61
7.10.4 Line Interface Unit ........................................................................................................................ 62
7.10.5 DS1 Synchronization Interface..................................................................................................... 68
7.10.6 E1 Synchronization Interface ....................................................................................................... 70
7.10.7 G.703 2048kHz Synchronization Interface................................................................................... 72
7.10.8 G.703 Appendix II 6312kHz Japanese Synchronization Interface............................................... 73
7.11 COMPOSITE CLOCK RECEIVERS AND TRANSMITTER ......................................................................74
7.11.1 IC1 and IC2 Receivers ................................................................................................................. 75
7.11.2 OC8 Transmitter ........................................................................................................................... 75
7.12 MICROPROCESSOR INTERFACES ..................................................................................................77
7.12.1 Parallel Interface Modes............................................................................................................... 77
7.12.2 SPI Interface Mode....................................................................................................................... 77
7.13 RESET LOGIC ..............................................................................................................................79
7.14 POWER-SUPPLY CONSIDERATIONS ..............................................................................................80
7.15 INITIALIZATION .............................................................................................................................80
8. REGISTER DESCRIPTIONS ...............................................................................................81
8.1 STATUS BITS ...............................................................................................................................81
8.2 CONFIGURATION FIELDS ..............................................................................................................81
8.3 MULTIREGISTER FIELDS ...............................................................................................................81
8.4 CORE REGISTER DEFINITIONS......................................................................................................82
8.5 BITS TRANSCEIVER REGISTER DEFINITIONS ..............................................................................147
9. JTAG TEST ACCESS PORT AND BOUNDARY SCAN....................................................198
9.1 JTAG DESCRIPTION ..................................................................................................................198
9.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ...........................................................199
9.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ....................................................................201
9.4 JTAG TEST REGISTERS ............................................................................................................202
10. ELECTRICAL CHARACTERISTICS..................................................................................203
10.1 DC CHARACTERISTICS ..............................................................................................................203
10.2 INPUT CLOCK TIMING .................................................................................................................207
10.3 OUTPUT CLOCK TIMING .............................................................................................................207
10.4 BITS TRANSCEIVER TIMING .......................................................................................................208
10.5 PARALLEL INTERFACE TIMING ....................................................................................................210
10.6 SPI INTERFACE TIMING..............................................................................................................213
10.7 JTAG INTERFACE TIMING ..........................................................................................................214
11. PIN ASSIGNMENTS ..........................................................................................................215
12. PACKAGE INFORMATION ...............................................................................................221
12.1 256-PIN CSBGA (17MM X 17MM) (56-G6017-001)....................................................................221
13. THERMAL INFORMATION................................................................................................222
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