and Deserializer. LM2502 Datasheet

LM2502 Deserializer. Datasheet pdf. Equivalent


National Semiconductor LM2502
www.DataSheet4U.com
August 2005
LM2502
Mobile Pixel Link (MPL) Display Interface Serializer and
Deserializer
General Description
The LM2502 device is a dual link display interface SERDES
that adapts existing CPU / video busses to a low power
current-mode serial MPL link. The chipset may also be used
for a RGB565 application with glue logic. The interconnect is
reduced from 22 signals to only 3 active signals with the
LM2502 chipset easing flex interconnect design, size and
cost.
The Master Serializer (SER) resides beside an application
processor or baseband processor and translates a parallel
bus from LVCMOS levels to serial MPL levels for transmis-
sion over a flex cable and PCB traces to the Slave Deseri-
alizer (DES) located near the display module.
Dual display support is provided for a primary and sub
display through the use of two ChipSelect signals. A Mode
pin selects either a i80 or m68 style interface.
The Power_Down (PD*) input controls the power state of the
MPL interface. When PD* is asserted, the MD1/0 and MC
signals are powered down to save current.
The LM2502 implements the physical layer of the MPL Stan-
dard (MPL-0). The LM2502 is offered in NOPB (Lead-free)
UFBGA and LLP packages.
Features
n >300 Mbps Dual Link Raw Throughput
n MPL Physical Layer (MPL-0)
n Pin selectable Master / Slave mode
n Frequency Reference Transport
n Complete LVCMOS / MPL Translation
n Interface Modes:
— 16-bit CPU, i80 or m68 style
— RGB565 with glue logic
n −30˚C to 85˚C Operating Range
n Link power down mode reduces IDDZ < 10 µA
n Dual Display Support (CS1* & CS2*)
n Via-less MPL interconnect feature
n 3.0V Supply Voltage (VDD and VDDA)
n Interfaces to 1.7V to 3.3V Logic (VDDIO)
System Benefits
n Small Interface
n Low Power
n Low EMI
n Frequency Reference Transport
n Intrinsic Level Translation
Typical Application Diagram
Ordering Information
NSID
LM2502SM
LM2502SQ
Package Type
49 Lead UFBGA style, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch
1000 std reel, LM2502SMX 4500 reel
40 Lead LLP style, 5.0 X 5.0 X 0.8 mm, 0.4 mm pitch
1000 std reel, LM2502SQX 4500 reel
20093301
Package ID
SLH49A
SQF40A
© 2005 National Semiconductor Corporation DS200933
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LM2502 Datasheet
Recommendation LM2502 Datasheet
Part LM2502
Description Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer
Feature LM2502; www.DataSheet4U.com August 2005 LM2502 Mobile Pixel Link (MPL) Display Interface Serializer and Des.
Manufacture National Semiconductor
Datasheet
Download LM2502 Datasheet




National Semiconductor LM2502
UFBGA Connection Diagram
TOP VIEW
(not to scale)
20093319
TABLE 1. Ball Assignment
Ball # Master Slave
Ball # Master Slave
A1 D0 D0
D5 NC NC
A2 D1 D1
A3 D2 D2
A4
VDDA
VDDA
A5 INTR CLKDIS*
D6
VSScore
VSScore
D7
VDDcore
VDDcore
E1 D8 D8
E2 D9 D9
A6
MD1
MD0
E3 NC NC
A7 MC MC
E4 NC NC
B1 D3 D3
E5 NC NC
B2 D4 D4
E6
CS1*
CS1*
B3 D5 D5
E7 PLLCON2 PLLCON2
B4
VSSA
VSSA
B5
M/S*
M/S*
F1 D10 D10
F2 D11 D11
B6
Mode
Mode
F3 D12 D12
B7
MD0
MD1
C1 D6 D6
F4
VSSIO
VSSIO
F5
MF0
MF0
C2 D7 D7
F6 PLLCON1 PLLCON1
C3 NC NC
F7 PD* PD*
C4 NC NC
G1 D13 D13
C5 NC NC
G2 D14 D14
C6
CS2*
CS2*
G3 D15 D15
C7
MF1
MF1
D1
VDDIO
VDDIO
D2
VSSIO
VSSIO
D3 NC NC
G4
VDDIO
VDDIO
G5 A/D A/D
G6 PLLCON0 PLLCON0
G7
CLK
CLK
D4 NC NC
NC = Not Connected
Note: Three pins are different between Master and Slave configurations - see also Figure 17
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National Semiconductor LM2502
LLP Connection Diagram
TOP VIEW
(not to scale)
20093324
TABLE 2. Pad Assignment
Pin # Master Slave
Ball # Master Slave
1 D0 D0
21
CLK
CLK
2 D3 D3
22 PD* PD*
3 D7 D7
23
CS1*
CS1*
4 D6 D6
24 PLLCON2 PLLCON2
5
VSSIO
VSSIO
6
VDDIO
VDDIO
7 D8 D8
25
VSScore
VSScore
26
VDDcore
VDDcore
27
MF1
MF1
8 D9 D9
28
CS2*
CS2*
9 D10 D10
10 D11 D11
29
MD0M
MD1S
30 MODE MODE
11 D13 D13
31 MC MC
12 D14 D14
13 D12 D12
32
MD1M
MD0S
33
M/S*
M/S*
14 D15 D15
15
VSSIO
VSSIO
16
VDDIO
VDDIO
17 A/D A/D
34 INTRM CLKDIS*S
35
VSSA
VSSA
36
VDDA
VDDA
37 D2 D2
18
MF0
MF0
38 D5 D5
19 PLLCON0 PLLCON0
39 D1 D1
20 PLLCON1 PLLCON1
40 D4 D4
DAP
GND
GND
DAP
GND
GND
Note: Three pins are different between Master and Slave configurations.
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