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Interface Unit. DS26303 Datasheet

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Interface Unit. DS26303 Datasheet






DS26303 Unit. Datasheet pdf. Equivalent




DS26303 Unit. Datasheet pdf. Equivalent





Part

DS26303

Description

Octal Line Interface Unit

Manufacture

Maxim Integrated Products

Datasheet
Download DS26303 Datasheet


Maxim Integrated Products DS26303

DS26303; www.DataSheet4U.com DS26303 3.3V, E1/T1 /J1, Short-Haul, Octal Line Interface U nit www.maxim-ic.com GENERAL DESCRIPTI ON The DS26303 is an 8-channel short-ha ul line interface unit (LIU) that suppo rts E1/T1/J1 from a single 3.3V power s upply. A wide variety of applications a re supported through internal terminati on or external termination. A single bi ll of material can.


Maxim Integrated Products DS26303

support E1/T1/J1 with minimum external components. Redundancy is supported thr ough nonintrusive monitoring, optimal h igh-impedance modes, and configurable 1 :1 or 1+1 backup enhancements. An on-ch ip synthesizer generates the E1/T1/J1 c lock rates by a single master clock inp ut of various frequencies. Two clock ou tput references are also offered. FEAT URES 8 Complete E1.


Maxim Integrated Products DS26303

, T1, or J1 Short-Haul Line Interface Un its Independent E1, T1, or J1 Selection s Internal Software-Selectable Transmit and Receive-Side Termination Crystal-L ess Jitter Attenuator Selectable Single -Rail and Dual-Rail Mode and AMI or HDB 3/B8ZS Line Encoding and Decoding Detec tion and Generation of AIS Digital/Anal og Loss-of-Signal Detection as per T1.2 31, G.775, and ETS.



Part

DS26303

Description

Octal Line Interface Unit

Manufacture

Maxim Integrated Products

Datasheet
Download DS26303 Datasheet




 DS26303
www.DataSheet4U.com
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26303 is an 8-channel short-haul line
interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A wide variety of
applications are supported through internal
termination or external termination. A single bill of
material can support E1/T1/J1 with minimum external
components. Redundancy is supported through
nonintrusive monitoring, optimal high-impedance
modes, and configurable 1:1 or 1+1 backup
enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of
various frequencies. Two clock output references are
also offered.
APPLICATIONS
T1 Digital Cross-Connects
ATM and Frame Relay Equipment
Wireless Base Stations
ISDN Primary Rate Interface
E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers
FUNCTIONAL DIAGRAM
Jtag
RTIP
RRING
TTTIP
TRING
Software Control,
Hardware Control
and JTAG
MODESEL
RLOS
Receiver
Transmitter
1
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
8
DS26303
DS26303
3.3V, E1/T1/J1, Short-Haul,
Octal Line Interface Unit
FEATURES
8 Complete E1, T1, or J1 Short-Haul Line
Interface Units
Independent E1, T1, or J1 Selections
Internal Software-Selectable Transmit and
Receive-Side Termination
Crystal-Less Jitter Attenuator
Selectable Single-Rail and Dual-Rail Mode
and AMI or HDB3/B8ZS Line Encoding and
Decoding
Detection and Generation of AIS
Digital/Analog Loss-of-Signal Detection as
per T1.231, G.775, and ETS 300 233
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock will be Internally
Adapted for T1 or E1 Use
Built-In BERT Tester for Diagnostics
8-Bit Parallel Interface Support for Intel or
Motorola Mode or a 4-Wire Serial Interface
Hardware Mode Interface Support
Transmit Short-Circuit Protection
G.772 Nonintrusive Monitoring
Specification Compliance to the Latest T1
and E1 Standards—ANSI T1.102, AT&T Pub
62411, T1.231, T1.403, ITU-T G.703, G.742,
G.775, G.823, ETS 300 166, and ETS 300 233
Single 3.3V Supply with 5V Tolerant I/O
JTAG Boundary Scan as per IEEE 1149.1
144-Pin eLQFP Package
ORDERING INFORMATION
PART
DS26303L-XXX
TEMP RANGE PIN-PACKAGE
0°C to +70°C 144 eLQFP
DS26303L-XXX+
0°C to +70°C 144 eLQFP
DS26303LN-XXX -40°C to +85°C 144 eLQFP
DS26303LN-XXX+ -40°C to +85°C 144 eLQFP
Note: When XXX is 075, the part defaults to 75Ω impedance in E1
mode; when XXX is 120, the part defaults to 120Ω impedance.
+ Denotes a lead-free/RoHS-compliant package.
e = Exposed Pad.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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 DS26303
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
TABLE OF CONTENTS
1 DETAILED DESCRIPTION ...............................................................................................................6
2 TELECOM SPECIFICATIONS COMPLIANCE.................................................................................7
3 BLOCK DIAGRAMS .........................................................................................................................9
4 PIN DESCRIPTION .........................................................................................................................11
4.1 HARDWARE AND HOST PORT OPERATION ......................................................................................20
4.1.1
4.1.2
4.1.3
4.1.4
Hardware Mode................................................................................................................................... 20
Serial Port Operation .......................................................................................................................... 21
Parallel Port Operation........................................................................................................................ 22
Interrupt Handling ............................................................................................................................... 22
5 REGISTERS ....................................................................................................................................24
5.1 REGISTER DESCRIPTION ...............................................................................................................29
5.1.1 Primary Registers................................................................................................................................ 29
5.1.2 Secondary Registers........................................................................................................................... 38
5.1.3 Individual LIU Registers ...................................................................................................................... 40
5.1.4 BERT Registers .................................................................................................................................. 47
6 FUNCTIONAL DESCRIPTION........................................................................................................54
6.1 POWER-UP AND RESET .................................................................................................................54
6.2 MASTER CLOCK ............................................................................................................................54
6.3 TRANSMITTER ...............................................................................................................................55
6.3.1 Transmit Line Templates .................................................................................................................... 56
6.3.2 LIU Transmit Front-End ...................................................................................................................... 58
6.3.3 Dual-Rail Mode ................................................................................................................................... 59
6.3.4 Single-Rail Mode................................................................................................................................. 59
6.3.5 Zero Suppression—B8ZS or HDB3 .................................................................................................... 59
6.3.6 Transmit Power-Down ........................................................................................................................ 59
6.3.7 Transmit All Ones................................................................................................................................ 59
6.3.8 Driver Fail Monitor............................................................................................................................... 59
6.4 RECEIVER .....................................................................................................................................59
6.4.1 Peak Detector and Slicer .................................................................................................................... 59
6.4.2 Clock and Data Recovery ................................................................................................................... 59
6.4.3 Loss of Signal...................................................................................................................................... 60
6.4.4 AIS ...................................................................................................................................................... 60
6.4.5 Bipolar Violation and Excessive Zero Detector................................................................................... 62
6.4.6 LIU Receiver Front-End ...................................................................................................................... 62
6.5 HITLESS-PROTECTION SWITCHING (HPS) ......................................................................................62
6.6 JITTER ATTENUATOR .....................................................................................................................64
6.7 G.772 MONITOR ...........................................................................................................................65
6.8 LOOPBACKS ..................................................................................................................................65
6.8.1 Analog Loopback ................................................................................................................................ 65
6.8.2 Digital Loopback.................................................................................................................................. 65
6.8.3 Remote Loopback............................................................................................................................... 66
6.8.4 Dual Loopback .................................................................................................................................... 67
6.9 BERT...........................................................................................................................................68
6.9.1
6.9.2
6.9.3
6.9.4
Configuration and Monitoring.............................................................................................................. 68
BERT Interrupt Handling..................................................................................................................... 69
Receive Pattern Detection .................................................................................................................. 69
Transmit Pattern Generation............................................................................................................... 71
7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................................72
7.1 TAP CONTROLLER STATE MACHINE ..............................................................................................73
7.1.1
7.1.2
7.1.3
7.1.4
Test-Logic-Reset................................................................................................................................. 73
Run-Test-Idle ...................................................................................................................................... 73
Select-DR-Scan .................................................................................................................................. 73
Capture-DR ......................................................................................................................................... 73
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 DS26303
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
7.1.5 Shift-DR............................................................................................................................................... 73
7.1.6 Exit1-DR.............................................................................................................................................. 73
7.1.7 Pause-DR............................................................................................................................................ 73
7.1.8 Exit2-DR.............................................................................................................................................. 73
7.1.9 Update-DR .......................................................................................................................................... 73
7.1.10 Select-IR-Scan .................................................................................................................................... 74
7.1.11 Capture-IR........................................................................................................................................... 74
7.1.12 Shift-IR ................................................................................................................................................ 74
7.1.13 Exit1-IR ............................................................................................................................................... 74
7.1.14 Pause-IR ............................................................................................................................................. 74
7.1.15 Exit2-IR ............................................................................................................................................... 74
7.1.16 Update-IR............................................................................................................................................ 74
7.2 INSTRUCTION REGISTER................................................................................................................76
7.2.1 EXTEST .............................................................................................................................................. 76
7.2.2 HIGHZ ................................................................................................................................................. 76
7.2.3 CLAMP................................................................................................................................................ 76
7.2.4 SAMPLE/PRELOAD ........................................................................................................................... 76
7.2.5 IDCODE .............................................................................................................................................. 76
7.2.6 BYPASS.............................................................................................................................................. 76
7.3 TEST REGISTERS ..........................................................................................................................77
7.3.1 Boundary Scan Register ..................................................................................................................... 77
7.3.2 Bypass Register .................................................................................................................................. 77
7.3.3 Identification Register ......................................................................................................................... 77
8 OPERATING PARAMETERS .........................................................................................................78
9 THERMAL CHARACTERISTICS....................................................................................................79
10 AC CHARACTERISTICS ................................................................................................................80
10.1 LINE INTERFACE CHARACTERISTICS...............................................................................................80
10.2 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS .................................................................81
10.3 SERIAL PORT ................................................................................................................................93
10.4 SYSTEM TIMING ............................................................................................................................94
10.5 JTAG TIMING................................................................................................................................96
11 PIN CONFIGURATION ...................................................................................................................97
11.1 144-PIN LQFP WITH EXPOSED PAD ..............................................................................................97
12 PACKAGE INFORMATION ............................................................................................................98
12.1 144-PIN LQFP WITH EXPOSED PAD PACKAGE OUTLINE (56-G6037-002) (SHEET 1 OF 2) ..............98
12.2 144-PIN LQFP WITH EXPOSED PAD PACKAGE OUTLINE (SHEET 2 OF 2).........................................99
13 DOCUMENT REVISION HISTORY...............................................................................................100
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