DatasheetsPDF.com

Interface Unit. DS26334 Datasheet

DatasheetsPDF.com

Interface Unit. DS26334 Datasheet






DS26334 Unit. Datasheet pdf. Equivalent




DS26334 Unit. Datasheet pdf. Equivalent





Part

DS26334

Description

E1/T1/J1 Shortand Long-Haul Line Interface Unit



Feature


www.DataSheet4U.com DS26334 3.3V, 16-Ch annel, E1/T1/J1 Shortand Long-Haul Line Interface Unit www.maxim-ic.com GENER AL DESCRIPTION The DS26334 is a 16-chan nel short/long-haul line interface unit (LIU) that supports E1/T1/J1 from a si ngle 3.3V power supply. A single bill o f material can support E1/T1/J1 that re quires no external termination. Redunda ncy is supported t.
Manufacture

Dallas Semiconductor

Datasheet
Download DS26334 Datasheet


Dallas Semiconductor DS26334

DS26334; hrough nonintrusive monitoring, optimal high-impedance modes and configurable 1 :1 or 1+1 backup enhancements. An on-ch ip synthesizer generates the E1/T1/J1 c lock rates by a single master clock inp ut of various frequencies. Two clock ou tput references are also offered. The d evice is offered in a 256-pin TE-CSBGA, the smallest package available for a 1 6-channel LIU. FE.


Dallas Semiconductor DS26334

ATURES 16 E1, T1, or J1 Short/Long-Haul Line Interface Units Independent E1, T1 or J1 Selections Fully Internal Impeda nce Match Requires No External Resistor s Software-Selectable Transmit and Rece iveSide Impedance Match Crystal-Less Ji tter Attenuator Selectable Single-Rail and Dual-Rail Mode and AMI or HDB3/B8ZS Line Encoding and Decoding Detection a nd Generation of A.


Dallas Semiconductor DS26334

IS Digital/Analog Loss of Signal Detecti on as per T1.231, G.775 and ETS 300 233 External Master Clock Can Be Multiple of 2.048MHz or 1.544MHz for T1/J1 or E1 Operation; This Clock Will Be Internal ly Adapted for T1 or E1 Usage Receiver Signal Level Indicator from -2.5dB to - 38dB in T1 Mode and -3dB to -43dB in E1 Mode in 2.5dB Increments Two Built-In BERT Testers for D.

Part

DS26334

Description

E1/T1/J1 Shortand Long-Haul Line Interface Unit



Feature


www.DataSheet4U.com DS26334 3.3V, 16-Ch annel, E1/T1/J1 Shortand Long-Haul Line Interface Unit www.maxim-ic.com GENER AL DESCRIPTION The DS26334 is a 16-chan nel short/long-haul line interface unit (LIU) that supports E1/T1/J1 from a si ngle 3.3V power supply. A single bill o f material can support E1/T1/J1 that re quires no external termination. Redunda ncy is supported t.
Manufacture

Dallas Semiconductor

Datasheet
Download DS26334 Datasheet




 DS26334
www.DataSheet4U.com
www.maxim-ic.com
DS26334
3.3V, 16-Channel, E1/T1/J1 Short-
and Long-Haul Line Interface Unit
GENERAL DESCRIPTION
The DS26334 is a 16-channel short/long-haul line
interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A single bill of material can
support E1/T1/J1 that requires no external
termination. Redundancy is supported through
nonintrusive monitoring, optimal high-impedance
modes and configurable 1:1 or 1+1 backup
enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of
various frequencies. Two clock output references are
also offered. The device is offered in a 256-pin
TE-CSBGA, the smallest package available for a
16-channel LIU.
APPLICATIONS
T1 Digital Cross-Connects
ATM and Frame Relay Equipment
Wireless Base Stations
ISDN Primary Rate Interface
E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers
FUNCTIONAL DIAGRAM
JTAG
SOFTWARE CONTROL
AND JTAG
MODE
LOSS
RTIP
RRING
TTIP
TRING
RECEIVER
TRANSMITTER
1
RPOS
RNEG
RCLK
TPOS
TNEG
TCLK
16
FEATURES
16 E1, T1, or J1 Short/Long-Haul Line
Interface Units
Independent E1, T1 or J1 Selections
Fully Internal Impedance Match Requires No
External Resistors
Software-Selectable Transmit and Receive-
Side Impedance Match
Crystal-Less Jitter Attenuator
Selectable Single-Rail and Dual-Rail Mode
and AMI or HDB3/B8ZS Line Encoding and
Decoding
Detection and Generation of AIS
Digital/Analog Loss of Signal Detection as
per T1.231, G.775 and ETS 300 233
External Master Clock Can Be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock Will Be Internally
Adapted for T1 or E1 Usage
Receiver Signal Level Indicator from -2.5dB to
-38dB in T1 Mode and -3dB to -43dB in E1
Mode in 2.5dB Increments
Two Built-In BERT Testers for Diagnostics
8-Bit Parallel Interface Support for Intel or
Motorola Mode or a 4-Wire Serial Interface
Transmit Short-Circuit Protection
G.772 Nonintrusive Monitoring
Receive Monitor Mode Handles Combinations
of 14dB to 30dB of Resistive Attenuation
Along with 12dB to 30dB of Cable Attenuation
Specification Compliance to the Latest T1
and E1 Standards—ANSI T1.102, AT&T Pub
62411, T1.231, T1.403, ITU-T G.703, G.742,
G.775, G.823, ETS 300 166, and ETS 300 233
Single 3.3V Supply with 5V Tolerant I/O
JTAG Boundary Scan as Per IEEE 1149.1
ORDERING INFORMATION
PART
DS26334G
DS26334GN
TEMP RANGE PIN-PACKAGE
0°C to +70°C 256 TE-CSBGA
-40°C to +85°C 256 TE-CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 121
REV: 053107




 DS26334
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
TABLE OF CONTENTS
1 STANDARDS COMPLIANCE ...........................................................................................................6
1.1 TELECOM SPECIFICATIONS COMPLIANCE..........................................................................................6
2 DETAILED DESCRIPTION ...............................................................................................................7
3 BLOCK DIAGRAMS .........................................................................................................................8
4 PIN DESCRIPTION .........................................................................................................................10
5 FUNCTIONAL DESCRIPTION........................................................................................................17
5.1 PORT OPERATION .........................................................................................................................17
5.1.1 Serial Port Operation .......................................................................................................................... 17
5.1.2 Parallel Port Operation........................................................................................................................ 18
5.1.3 Interrupt Handling ............................................................................................................................... 18
5.2 POWER-UP AND RESET .................................................................................................................19
5.3 MASTER CLOCK ............................................................................................................................19
5.4 TRANSMITTER ...............................................................................................................................20
5.4.1 Transmit Line Templates .................................................................................................................... 22
5.4.2 LIU Transmit Front-End ...................................................................................................................... 25
5.4.3 Transmit Dual-Rail Mode .................................................................................................................... 26
5.4.4 Transmit Single-Rail Mode.................................................................................................................. 26
5.4.5 Zero Suppression—B8ZS or HDB3 .................................................................................................... 26
5.4.6 Transmit Power-Down ........................................................................................................................ 26
5.4.7 Transmit All Ones................................................................................................................................ 27
5.4.8 Driver Fail Monitor............................................................................................................................... 27
5.5 RECEIVER .....................................................................................................................................27
5.5.1 Receiver Impedance Matching Calibration ......................................................................................... 27
5.5.2 Receiver Monitor Mode....................................................................................................................... 27
5.5.3 Peak Detector and Slicer .................................................................................................................... 28
5.5.4 Receive Level Indicator....................................................................................................................... 28
5.5.5 Clock and Data Recovery ................................................................................................................... 28
5.5.6 Loss of Signal...................................................................................................................................... 28
5.5.7 AIS ...................................................................................................................................................... 29
5.5.8 Receive Dual-Rail Mode ..................................................................................................................... 30
5.5.9 Receive Single-Rail Mode................................................................................................................... 30
5.5.10 Bipolar Violation and Excessive Zero Detector................................................................................... 30
5.6 JITTER ATTENUATOR .....................................................................................................................31
5.7 G.772 MONITOR ...........................................................................................................................32
5.8 LOOPBACKS ..................................................................................................................................32
5.8.1 Analog Loopback ................................................................................................................................ 32
5.8.2 Digital Loopback.................................................................................................................................. 33
5.8.3 Remote Loopback............................................................................................................................... 33
5.9 BERT...........................................................................................................................................34
5.9.1 General Description ............................................................................................................................ 34
5.9.2 Configuration and Monitoring.............................................................................................................. 35
5.9.3 Receive Pattern Detection .................................................................................................................. 36
5.9.4 Transmit Pattern Generation............................................................................................................... 38
6 REGISTER MAPS AND DEFINITION.............................................................................................39
6.1 REGISTER DESCRIPTION ...............................................................................................................48
6.1.1 Primary Register Bank ........................................................................................................................ 48
6.1.2 Secondary Register Bank ................................................................................................................... 63
6.1.3 Individual LIU Register Bank............................................................................................................... 66
6.1.4 BERT Registers .................................................................................................................................. 85
7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT ...................................92
7.1 TAP CONTROLLER STATE MACHINE ..............................................................................................93
7.1.1 Test-Logic-Reset................................................................................................................................. 93
7.1.2 Run-Test-Idle ...................................................................................................................................... 93
2 of 121




 DS26334
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
7.1.3 Select-DR-Scan .................................................................................................................................. 93
7.1.4 Capture-DR ......................................................................................................................................... 93
7.1.5 Shift-DR............................................................................................................................................... 93
7.1.6 Exit1-DR.............................................................................................................................................. 93
7.1.7 Pause-DR............................................................................................................................................ 93
7.1.8 Exit2-DR.............................................................................................................................................. 93
7.1.9 Update-DR .......................................................................................................................................... 93
7.1.10 Select-IR-Scan .................................................................................................................................... 94
7.1.11 Capture-IR........................................................................................................................................... 94
7.1.12 Shift-IR ................................................................................................................................................ 94
7.1.13 Exit1-IR ............................................................................................................................................... 94
7.1.14 Pause-IR ............................................................................................................................................. 94
7.1.15 Exit2-IR ............................................................................................................................................... 94
7.1.16 Update-IR............................................................................................................................................ 94
7.2 INSTRUCTION REGISTER................................................................................................................96
7.2.1 EXTEST .............................................................................................................................................. 96
7.2.2 HIGHZ ................................................................................................................................................. 96
7.2.3 CLAMP................................................................................................................................................ 96
7.2.4 SAMPLE/PRELOAD ........................................................................................................................... 96
7.2.5 IDCODE .............................................................................................................................................. 96
7.2.6 BYPASS.............................................................................................................................................. 96
7.3 TEST REGISTERS ..........................................................................................................................97
7.3.1 Boundary Scan Register ..................................................................................................................... 97
7.3.2 Bypass Register .................................................................................................................................. 97
7.3.3 Identification Register ......................................................................................................................... 97
8 DC ELECTRICAL CHARACTERIZATION......................................................................................98
8.1 DC PIN LOGIC LEVELS ..................................................................................................................98
8.2 SUPPLY CURRENT AND OUTPUT VOLTAGE .....................................................................................98
9 AC TIMING CHARACTERISTICS...................................................................................................99
9.1 LINE INTERFACE CHARACTERISTICS...............................................................................................99
9.2 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS ...............................................................100
9.3 SERIAL PORT ..............................................................................................................................112
9.4 SYSTEM TIMING ..........................................................................................................................113
9.5 JTAG TIMING..............................................................................................................................115
10 PIN CONFIGURATION .................................................................................................................116
11 PACKAGE INFORMATION ..........................................................................................................117
11.1 256-BALL TE-CSBGA (17MM X 17MM) (56-G6028-001) .............................................................117
12 THERMAL INFORMATION...........................................................................................................118
13 DATA SHEET REVISION HISTORY.............................................................................................120
3 of 121






Recommended third-party DS26334 Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)