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MOS FET. NP160N04TDG Datasheet

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MOS FET. NP160N04TDG Datasheet






NP160N04TDG FET. Datasheet pdf. Equivalent




NP160N04TDG FET. Datasheet pdf. Equivalent





Part

NP160N04TDG

Description

SWITCHING N-CHANNEL POWER MOS FET



Feature


www.DataSheet4U.com DATA SHEET MOS FIE LD EFFECT TRANSISTOR NP160N04TDG SWIT CHING N-CHANNEL POWER MOS FET DESCRIPT ION The NP160N04TDG is N-channel MOS Fi eld Effect Transistor designed for high current switching applications. ORDER ING INFORMATION PART NUMBER NP160N04TDG -E1-AY NP160N04TDG-E2-AY Note Note LEA D PLATING Pure Sn (Tin) PACKING Tape 8 00 p/reel PACKAGE.
Manufacture

NEC

Datasheet
Download NP160N04TDG Datasheet


NEC NP160N04TDG

NP160N04TDG; TO-263-7pin (MP-25ZT) typ. 1.5 g Note Pb-free (This product does not contain Pb in the external electrode). FEATURE S • Super low on-state resistance RDS (on)1 = 1.6 mΩ TYP. / 2.0 mΩ MAX. (VG S = 10 V, ID = 80 A) RDS(on)2 = 2.2 mΩ TYP. / 5.4 mΩ MAX. (VGS = 4.5 V, ID = 80 A) • High Current Rating ID(DC) = ±160 A • Logic level drive type (TO -263-7pin) ABSOLUTE MAXIMUM .


NEC NP160N04TDG

RATINGS (TA = 25°C) Drain to Source Vol tage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) (TC = 2 5°C) Drain Current (pulse) Note1 VDSS VGSS ID(DC) ID(pulse) PT1 PT2 Tch Tstg 40 ±20 ±160 ±640 220 1.8 175 −55 to +175 372 61 372 V V A A W W °C ° C mJ A mJ Total Power Dissipation (TC = 25°C) Total Power Dissipation (TA = 25°C) Channel Temperature St.


NEC NP160N04TDG

orage Temperature Single Avalanche Energ y Note2 Note3 Note3 EAS IAR EAR Repet itive Avalanche Current Repetitive Aval anche Energy Notes 1. PW ≤ 10 μs, D uty Cycle ≤ 1% 2. Starting Tch = 25° C, VDD = 20 V, RG = 25 Ω, VGS = 20 → 0 V, L = 100 μH 3. RG = 25 Ω, Tch(pe ak) ≤ 150°C THERMAL RESISTANCE Chan nel to Case Thermal Resistance Channel to Ambient Thermal Resistance Rt.

Part

NP160N04TDG

Description

SWITCHING N-CHANNEL POWER MOS FET



Feature


www.DataSheet4U.com DATA SHEET MOS FIE LD EFFECT TRANSISTOR NP160N04TDG SWIT CHING N-CHANNEL POWER MOS FET DESCRIPT ION The NP160N04TDG is N-channel MOS Fi eld Effect Transistor designed for high current switching applications. ORDER ING INFORMATION PART NUMBER NP160N04TDG -E1-AY NP160N04TDG-E2-AY Note Note LEA D PLATING Pure Sn (Tin) PACKING Tape 8 00 p/reel PACKAGE.
Manufacture

NEC

Datasheet
Download NP160N04TDG Datasheet




 NP160N04TDG
www.DataSheet4U.com
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP160N04TDG
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
The NP160N04TDG is N-channel MOS Field Effect Transistor designed for high current switching applications.
ORDERING INFORMATION
PART NUMBER
NP160N04TDG-E1-AY Note
NP160N04TDG-E2-AY Note
LEAD PLATING
Pure Sn (Tin)
PACKING
Tape 800 p/reel
Note Pb-free (This product does not contain Pb in the external electrode).
PACKAGE
TO-263-7pin (MP-25ZT) typ. 1.5 g
FEATURES
Super low on-state resistance
RDS(on)1 = 1.6 mΩ TYP. / 2.0 mΩ MAX. (VGS = 10 V, ID = 80 A)
RDS(on)2 = 2.2 mΩ TYP. / 5.4 mΩ MAX. (VGS = 4.5 V, ID = 80 A)
High Current Rating
ID(DC) = ±160 A
Logic level drive type
(TO-263-7pin)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
Gate to Source Voltage (VDS = 0 V)
VGSS
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
ID(DC)
ID(pulse)
Total Power Dissipation (TC = 25°C)
PT1
Total Power Dissipation (TA = 25°C)
PT2
Channel Temperature
Tch
Storage Temperature
Single Avalanche Energy Note2
Repetitive Avalanche Current Note3
Repetitive Avalanche Energy Note3
Tstg
EAS
IAR
EAR
40
±20
±160
±640
220
1.8
175
55 to +175
372
61
372
V
V
A
A
W
W
°C
°C
mJ
A
mJ
Notes 1. PW 10 μs, Duty Cycle 1%
2. Starting Tch = 25°C, VDD = 20 V, RG = 25 Ω, VGS = 20 0 V, L = 100 μH
3. RG = 25 Ω, Tch(peak) 150°C
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
0.68
83.3
°C/W
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D18761EJ2V0DS00 (2nd edition)
Date Published July 2007 NS CP(K)
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
2007




 NP160N04TDG
NP160N04TDG
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
IDSS VDS = 40 V, VGS = 0 V
Gate Leakage Current
IGSS VGS = ±20 V, VDS = 0 V
Gate to Source Threshold Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
VGS(th)
| yfs |
RDS(on)1
VDS = VGS, ID = 250 μA
VDS = 5 V, ID = 40 A
VGS = 10 V, ID = 80 A
<R>
<R>
<R>
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
RDS(on)2
Ciss
Coss
Crss
VGS = 4.5 V, ID = 80 A
VDS = 25 V,
VGS = 0 V,
f = 1 MHz
Turn-on Delay Time
td(on)
VDD = 20 V, ID = 80 A,
Rise Time
tr VGS = 10 V,
Turn-off Delay Time
td(off)
RG = 0 Ω
Fall Time
Total Gate Charge Note
tf
QG VDD = 32 V,
Gate to Source Charge
QGS VGS = 10 V,
Gate to Drain Charge
Body Diode Forward Voltage Note
QGD
VF(S-D)
ID = 160 A
IF = 160 A, VGS = 0 V
Reverse Recovery Time
trr IF = 160 A, VGS = 0 V,
Reverse Recovery Charge
Note Pulsed test
Qrr di/dt = 100 A/μs
MIN.
1.5
37
TYP. MAX.
1
±100
2.0 2.5
94
1.6 2.0
2.2 5.4
10500 15750
980 1470
630 1140
35 80
55 140
107 220
17 50
180 270
30
57
0.9 1.5
49
60
UNIT
μA
nA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
PG.
VGS = 20 0 V
50 Ω
L
VDD
BVDSS
ID
VDD
IAS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 μs
Duty Cycle 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
Wave Form
0
td(on)
VGS 90%
90%
10% 10%
tr td(off) tf
ton toff
D.U.T.
IG = 2 mA
PG. 50 Ω
RL
VDD
2 Data Sheet D18761EJ2V0DS




 NP160N04TDG
NP160N04TDG
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
120
100
80
60
40
20
0
0 25 50 75 100 125 150 175
TC - Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
10000
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
250
200
150
100
50
0
0 25 50 75 100 125 150 175
TC - Case Temperature - °C
1000
100
10
RD(SV(oGnS)
Limit
= 1i0
ed
V)
ID(pulse)
ID(DC) DC
PW
= 1i00 μs
1
TC = 25°C
Single Pulse
0.1
0.01 0.1
1
10
VDS - Drain to Source Voltage - V
100
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
100
Rth(ch-A) = 83.3°C/Wi
10
1
Rth(ch-C) = 0.68°C/Wi
0.1
Single Pulse
0.01
100 μ 1 m 10 m 100 m 1
10
PW - Pulse Width - s
100 1000
Data Sheet D18761EJ2V0DS
3






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