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INTEGRATED CIRCUIT. UPD12115 Datasheet

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INTEGRATED CIRCUIT. UPD12115 Datasheet






UPD12115 CIRCUIT. Datasheet pdf. Equivalent




UPD12115 CIRCUIT. Datasheet pdf. Equivalent





Part

UPD12115

Description

MOS INTEGRATED CIRCUIT



Feature


www.DataSheet4U.com DATA SHEET MOS INT EGRATED CIRCUIT μ PD12115 1.5 V/1.0 A GENERAL-PURPOSE CMOS REGULATOR DESCRI PTION μ PD12115 is a general-purpose C MOS regulator which has 1.5 V output vo ltage and 1.0 A output current capacity . This product is suitable for low powe r-supply-voltage LSI etc. By ON/OFF fun ction, the power consumption can be kep t low level at the t.
Manufacture

NEC

Datasheet
Download UPD12115 Datasheet


NEC UPD12115

UPD12115; ime of off-state. FEATURES • Output C urrent: 1.0 A • Output Voltage: 1.5 V (Fixed type) • Output Voltage Tolera nce: VO ± 2.0% (TJ = 25°C) • Dropou t Voltage: VDIF = 1.0 V MAX. (IO = 1.0 A) • Quiescent Current: 150 μ A TYP. (IO = 0 A) • Standby Current: 1 μ A • Available for laminated ceramic ca pacitor: (Electric capacity 10 μ F or higher) • On-chip over-current protec.


NEC UPD12115

tion circuit • On-chip thermal shut do wn circuit PIN CONFIGURATION (Marking Side) 5-PIN TO-252 (5-PIN MP-3ZK) 6 1. INPUT 2. ON/OFF 3. GND Note 1 2 3 4 5 4. NC 5. OUTPUT 6. GND (Fin) APPLICA TIONS Note No.3 pin is cut and can not be connected to substrate. No.6 is Fin and common to GND pin. This regulator is suitable for low power-supply-volta ge LSI which is used.


NEC UPD12115

in digital appliances etc. BLOCK DIAGR AM VIN ON/OFF ON/OFF − Buffer + − Error amp. + Over-current protection V OUT Constant Current Reference voltag e Thermal shut down Triming GND The in formation in this document is subject t o change without notice. Before using t his document, please confirm that this is the latest version. Not all product s and/or types are ava.

Part

UPD12115

Description

MOS INTEGRATED CIRCUIT



Feature


www.DataSheet4U.com DATA SHEET MOS INT EGRATED CIRCUIT μ PD12115 1.5 V/1.0 A GENERAL-PURPOSE CMOS REGULATOR DESCRI PTION μ PD12115 is a general-purpose C MOS regulator which has 1.5 V output vo ltage and 1.0 A output current capacity . This product is suitable for low powe r-supply-voltage LSI etc. By ON/OFF fun ction, the power consumption can be kep t low level at the t.
Manufacture

NEC

Datasheet
Download UPD12115 Datasheet




 UPD12115
www.DataSheet4U.com
DATA SHEET
MOS INTEGRATED CIRCUIT
μ PD12115
1.5 V/1.0 A GENERAL-PURPOSE
CMOS REGULATOR
DESCRIPTION
μ PD12115 is a general-purpose CMOS regulator which has 1.5 V output voltage and 1.0 A output current capacity.
This product is suitable for low power-supply-voltage LSI etc. By ON/OFF function, the power consumption can be
kept low level at the time of off-state.
FEATURES
PIN CONFIGURATION (Marking Side)
Output Current: 1.0 A
Output Voltage: 1.5 V (Fixed type)
5-PIN TO-252 (5-PIN MP-3ZK)
Output Voltage Tolerance: VO ± 2.0% (TJ = 25°C)
6 1. INPUT
Dropout Voltage: VDIF = 1.0 V MAX. (IO = 1.0 A)
2. ON/OFF
Quiescent Current: 150 μ A TYP. (IO = 0 A)
3. GND Note
Standby Current: 1 μ A
Available for laminated ceramic capacitor: (Electric capacity 10 μ F or higher)
1 2 345
4. NC
5. OUTPUT
On-chip over-current protection circuit
6. GND (Fin)
On-chip thermal shut down circuit
Note No.3 pin is cut and can not be connected
to substrate. No.6 is Fin and common to
APPLICATIONS
GND pin.
This regulator is suitable for low power-supply-voltage LSI which is used in digital appliances etc.
BLOCK DIAGRAM
ON/OFF
VIN
ON/OFF
Buffer
+
Constant Reference
Current
voltage
Over-current
protection
Error
amp.
+
VOUT
Triming
Thermal
shut down
GND
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G18851EJ1V0DS00 (1st edition)
Date Published July 2007 NS
Printed in Japan
2007




 UPD12115
μ PD12115
ORDERING INFORMATION
Part Number
Package
Output Voltage
Type
Marking
μ PD12115T1F
5-PIN TO-252 (5-PIN MP-3ZK)
1.5 V
Fixed
12115
Remark Since it is the tape-packaged product, “-E1” or “-E2” is added to the end of its product name.
Part Number
Package
Package Type
μ PD12115T1F-E1-AT Note
5-PIN TO-252 (5-PIN MP-3ZK)
16 mm wide embossed taping
Pin 1 on draw-out side
μ PD12115T1F-E2-AT Note
5-PIN TO-252 (5-PIN MP-3ZK)
2,500 pcs/reel
16 mm wide embossed taping
Pin 1 at take-up side
2,500 pcs/reel
Note Pb-free (This product does not contain Pb in the external electrode and other parts.)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise specified)
Parameter
Symbol
Rating
Unit
Input Voltage
ON/OFF Pin Voltage
Internal Power Dissipation (TC = 25°C) Note
Operating Ambient Temperature
VIN
VON/OFF
PT
TA
0.3 to +6.0
0.3 to VIN
10
40 to +85
V
V
W
°C
Operating Junction Temperature
TJ
40 to +150
°C
Storage Temperature
Tstg
55 to +150
°C
Thermal Resistance (junction to ambient)
Rth(J-A)
125 °C/W
Thermal Resistance (junction to case)
Rth(J-C)
12.5
°C/W
Note Internally limited. When the operating junction temperature rises above 150°C, the internal circuit shuts down
the output voltage.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
TYPICAL CONNECTION
ON/OFF
INPUT
CIN
INPUT
D1
μ PD12115
GND
GND
OUTPUT
COUT
OUTPUT
D2
2 Data Sheet G18851EJ1V0DS




 UPD12115
μ PD12115
CIN : 0.1 μ F or higher. Be sure to connect CIN to prevent parasitic oscillation. Set this value according to the length
of the line between the regulator and the INPUT pin. Use of a film capacitor or other capacitor with first-rate
voltage and temperature characteristics is recommended. If using a laminated ceramic capacitor, it is necessary
to ensure that CIN is 0.1 μ F or higher for the voltage and temperature range to be used.
COUT: 10 μ F or higher. Be sure to connect COUT to prevent oscillation and improve excessive load regulation. Place
CIN and COUT as close as possible to the IC pins (within 1 to 2 cm). Also, in case of using a laminated ceramic
capacitor, please note following items.
It is necessary to ensure that COUT is 10 μ F or higher for the voltage and temperature range to be used.
In case of using laminated ceramic capacitor, it is easy to become state of parasitic oscillation. Because ESR
of laminated ceramic capacitor is very low. Therefore, the capacitor and load condition (output current) which
fulfill the condition of the stable operation area of ESR shown below are recommended.
Stable Operation Area as below is regulated under condition of which this product is not on a substrate.
Therefore impedance on substrate is not considered.
D1 : If the OUTPUT pin has a higher voltage than the INPUT pin, connect a diode.
D2 : If the OUTPUT pin has a lower voltage than the GND pin, connect a Schottky barrier diode.
Caution Make sure that no external voltage is applied to the OUTPUT pin.
μ PD12115 COUT ESR Stable Operation Area
Unstable Operation Area
10
1 Stable Operation Area
0.1
Unstable Operation Area
0.01
0
200 400 600 800 1000
IO (mA)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Input Voltage
VIN 2.5
5.5 V
ON/OFF Pin Voltage
Output Current
Operating Ambient Temperature
VON/OFF
IO
TA
0
0
40
VIN V
1.0 A
+ 85 °C
Operating Junction Temperature
TJ
40
+ 125
°C
Caution1. Turn on VIN and VON/OFF at the same time, or turn on VIN first and then VON/OFF.
Turn off VIN and VON/OFF at the same time, or turn off VON/OFF first and then VIN.
2. If absolute maximum rating is not exceeded, you can used this product above the recommended
operating range. However, since a margin with absolute maximum rating decreases, please use
this product after sufficient evaluation.
Data Sheet G18851EJ1V0DS
3






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