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UPD720114 Dataheets PDF



Part Number UPD720114
Manufacturers NEC
Logo NEC
Description MOS INTEGRATED CIRCUIT
Datasheet UPD720114 DatasheetUPD720114 Datasheet (PDF)

www.DataSheet4U.com DATA SHEET MOS INTEGRATED CIRCUIT μPD720114 ECOUSBTM Series USB 2.0 HUB CONTROLLER The μPD720114 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision 2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports. The μPD720114 works backward compatible either when any one of the downstream ports is connected to a USB 1.1 compliant device, or when the upstream port is connected .

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www.DataSheet4U.com DATA SHEET MOS INTEGRATED CIRCUIT μPD720114 ECOUSBTM Series USB 2.0 HUB CONTROLLER The μPD720114 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision 2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports. The μPD720114 works backward compatible either when any one of the downstream ports is connected to a USB 1.1 compliant device, or when the upstream port is connected to a USB 1.1 compliant host. Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing. μPD720114 User’s Manual: S17463E FEATURES • Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps) • High-speed or full-speed packet protocol sequencer for Endpoint 0/1 • 4 (Max.) downstream facing ports • Low power consumption (10 μA when hub in idle status, 149 mA when all parts run in HS mode) • All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction. • Supports split transaction to handle full-speed and low-speed transaction on downstream facing ports when Hub controller is working in high-speed mode. • One Transaction Translator per Hub and supports four non-periodic buffers • Supports self-powered and bus-powered mode • Supports individual or global over-current detection and individual or ganged power control • Supports downstream port status with LED • Supports non-removable devices by I/O pin configuration • Support Energy Star for PC peripheral system • On chip Rpu, Rpd resistors and regulator (for core logic) • Use 30 MHz crystal • 3.3 V power supply The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S17462EJ4V0DS00 (4th edition) Date Published June 2007 NS Printed in Japan The mark "" shows major revised points. 2005 μPD720114 ORDERING INFORMATION Part Number Package 48-pin plastic TQFP (Fine pitch) (7 × 7) 48-pin plastic TQFP (Fine pitch) (7 × 7) Remark Lead-free product Lead-free product μPD720114GA-9EU-A μPD720114GA-YEU-A BLOCK DIAGRAM To Host/Hub downstream facing port Upstream facing port UP_PHY CDR SERDES UPC FS_REP SIE_2H ALL_TT F_TIM EP1 EP0 CDR DP(1)_PHY Downstream facing port #1 DP(2)_PHY DPC Downstream facing port #2 DP(3)_PHY Downstream facing port #3 To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port APLL X1/X2 OSB DP(4)_PHY Downstream facing port #4 2.5V REG CSB(4:1) PPB(4:1) 2 Data Sheet S17462EJ4V0DS μPD720114 APLL ALL_TT : Generates all clocks of Hub. : Translates the high-speed transactions (split transactions) for full/low-speed device to full/low-speed transactions. ALL_TT buffers the data transfer from either upstream or downstream direction. For OUT transaction, ALL_TT buffers data from upstream port and sends it out to the downstream facing ports after speed conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers data from downstream ports and sends it out to the upstream facing ports after speed conversion from full/low-speed to high-speed. CDR DPC DP(n)_PHY EP0 EP1 F_TIM (Frame Timer) : Data & clock recovery circuit : Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and Resume : Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction : Endpoint 0 controller : Endpoint 1 controller : Manages hub’s synchronization by using micro-SOF which is received at upstream port, and generates SOF packet when full/low-speed device is attached to FS_REP OSB 2.5V REG SERDES SIE_2H UP_PHY UPC downstream facing port. : Full/low-speed repeater is enabled when the μPD720114 are worked at full-speed mode : Oscillator Block : On chip 2.5V regulator : Serializer and Deserializer : Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer. : Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps) transaction : Upstream Port Controller handles Suspend and Resume Data Sheet S17462EJ4V0DS 3 μPD720114 PIN CONFIGURATION (TOP VIEW) • 48-pin plastic TQFP (Fine pitch) (7 × 7) μPD720114GA-9EU-A μPD720114GA-YEU-A VDD33REG VBUSM CSB1 PPB1 CSB2 PPB2 VSS CSB3 PPB3 CSB4 PPB4 SYSRSTB 48 47 46 45 44 43 42 41 40 39 38 37 VDD25OUT VSSREG LED4 LED3 LED2 LED1 GREEN AMBER VDD33 X1 X2 VDD25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 VSS DP4 DM4 VDD25 DP3 DM3 VDD33 DP2 DM2 VSS DP1 DM1 4 BUS_B TEST RREF AVSS(R) AVDD AVSS AVDD VDD33 DMU DPU VSS VDD25 Data Sheet S17462EJ4V0DS μPD720114 P.


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