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and Buffer. AZ100EL16VO Datasheet

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and Buffer. AZ100EL16VO Datasheet






AZ100EL16VO Buffer. Datasheet pdf. Equivalent




AZ100EL16VO Buffer. Datasheet pdf. Equivalent





Part

AZ100EL16VO

Description

ECL/PECL Oscillator Gain Stage and Buffer



Feature


www.DataSheet4U.com ARIZONA MICROTEK, I NC. AZ10EL16VO AZ100EL16VO ECL/PECL Os cillator Gain Stage and Buffer with Ena ble FEATURES • • • • • • Green and RoHS Compliant Available 25 0ps Propagation Delay on Q ¯ Output Hi gh Voltage Gain vs. Standard EL16 For O scillator Applications Available in 2x2 or 3x3mm MLP Package 75kΩ Enable Pull -Down Resistor S–Parameter (.s2p) .
Manufacture

AZM

Datasheet
Download AZ100EL16VO Datasheet


AZM AZ100EL16VO

AZ100EL16VO; and IBIS Model Files Available on Arizon a Microtek Website DESCRIPTION The AZ1 0/100EL16VO is an oscillator gain stage with a high gain output buffer includi ng an enable. The QHG/Q ¯ HG outputs h ave a voltage gain several times greate r than the Q/Q ¯ outputs. An enable in put (EN ¯¯ ) allows continuous oscill ator operation. When EN ¯¯ is LOW or floating (NC), input dat.


AZM AZ100EL16VO

a is passed to both sets of outputs. Whe n EN ¯¯ is HIGH, the QHG/Q ¯ HG outp uts will be forced LOW/HIGH respectivel y, while input data will continue to be passed to the Q/Q ¯ outputs. The EN ¯ input can be driven with an ECL/PEC L signal or a CMOS logic signal. The in put impedance of the D/D ¯ inputs rema in constant for all operating modes sin ce forcing the outputs vi.


AZM AZ100EL16VO

a the EN ¯¯ pin does not power-down th e chip but only disables the high gain QHG/Q ¯ HG outputs. Input protection d iodes are included on the D/D ¯ inputs for enhanced ESD protection. The EL16V O also provides a VBB output that suppo rts 1.5mA sink/source current. When use d, the VBB pin should be bypassed to gr ound or VCC via a 0.01μF capacitor. An y used output must have.

Part

AZ100EL16VO

Description

ECL/PECL Oscillator Gain Stage and Buffer



Feature


www.DataSheet4U.com ARIZONA MICROTEK, I NC. AZ10EL16VO AZ100EL16VO ECL/PECL Os cillator Gain Stage and Buffer with Ena ble FEATURES • • • • • • Green and RoHS Compliant Available 25 0ps Propagation Delay on Q ¯ Output Hi gh Voltage Gain vs. Standard EL16 For O scillator Applications Available in 2x2 or 3x3mm MLP Package 75kΩ Enable Pull -Down Resistor S–Parameter (.s2p) .
Manufacture

AZM

Datasheet
Download AZ100EL16VO Datasheet




 AZ100EL16VO
www.DataSheet4U.com
AZ10EL16VO
AZ100EL16VO
ARIZONA MICROTEK, INC.
ECL/PECL Oscillator Gain Stage and Buffer with Enable
FEATURES
Green and RoHS Compliant Available
250ps Propagation Delay on Q¯ Output
High Voltage Gain vs. Standard EL16
For Oscillator Applications
Available in 2x2 or 3x3mm MLP Package
75kΩ Enable Pull-Down Resistor
S–Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek Website
DESCRIPTION
The AZ10/100EL16VO is an oscillator gain stage with a high gain output buffer including an enable. The
QHG/Q¯ HG outputs have a voltage gain several times greater than the Q/Q¯ outputs. An enable input (E¯N¯ ) allows
continuous oscillator operation. When E¯N¯ is LOW or floating (NC), input data is passed to both sets of outputs.
When E¯N¯ is HIGH, the QHG/Q¯ HG outputs will be forced LOW/HIGH respectively, while input data will continue to
be passed to the Q/Q¯ outputs. The E¯N¯ input can be driven with an ECL/PECL signal or a CMOS logic signal.
The input impedance of the D/D¯ inputs remain constant for all operating modes since forcing the outputs via the
E¯N¯ pin does not power-down the chip but only disables the high gain QHG/Q¯ HG outputs.
Input protection diodes are included on the D/D¯ inputs for enhanced ESD protection.
The EL16VO also provides a VBB output that supports 1.5mA sink/source current. When used, the VBB pin
should be bypassed to ground or VCC via a 0.01μF capacitor.
Any used output must have an external pull down resistor. For 3.3V operation, an 180resistor to VEE is
recommended if an AC coupled load is present. At 5.0V, a 330resistor is recommended for the AC load case.
Alternately, a 50load terminated to VCC – 2V or the Thevenin equivalent may be driven directly. Unused outputs
may be left floating (NC).
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
PIN/PAD DESCRIPTION
Q
PIN FUNCTION
Q D/D¯ Data Inputs
Q/Q¯ Data Outputs
D QHG QHG/Q¯ HG Data Outputs w/High Gain
VBB Reference Voltage Output
D
QHG E¯N¯
Enable Input
VCC Positive Supply
EN VEE Negative Supply
VBB
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com




 AZ100EL16VO
AZ10EL16VO
AZ100EL16VO
PACKAGE AVAILABILITY
PACKAGE
PART NUMBER MARKING NOTES
MLP 8 (2x2) Green / RoHS
Compliant / Lead (Pb) Free
AZ100EL16VONG
P0G
<Date Code>
1,2
MLP 8 (2x2)
AZ100EL16VONB
P4
<Date Code>
1,2,3
MLP 8 (2x2) RoHS Compliant /
Lead (Pb) Free
AZ100EL16VONB+
P4+
<Date Code>
1,2
MLP 8 (2x2x0.75) Green / RoHS
Compliant / Lead (Pb) Free
AZ100EL16VONBG
P4G
<Date Code>
1,2
AZM
MLP 16 (3x3)
AZ10/100EL16VOL 16J
1,2
<Date Code>
MLP 16 (3x3) Green / RoHS
Compliant / Lead (Pb) Free
AZ10/100EL16VOLG
AZMG
16J
<Date Code>
1,2
SOIC 8
AZ10EL16VOD
AZM10
EL16VO
1,2,4
SOIC 8
AZ100EL16VOD
AZM100
EL16VO
1,2,4
TSSOP 8
AZ10EL16VOT
AZT
16VO
1,2,4
TSSOP 8 RoHS Compliant / Lead
(Pb) Free
AZ10EL16VOT+
AZT+
16VO
1,2,4
TSSOP 8
AZ100EL16VOT
AZH
16VO
1,2,4
TSSOP 8 RoHS Compliant / Lead
(Pb) Free
AZ100EL16VOT+
AZH+
16VO
1,2,4
TSSOP 10 RoHS Compliant / Lead
(Pb) Free
AZ10EL16VOU+
AZT+
16VOU
1,2,4
TSSOP 10 RoHS Compliant / Lead
(Pb) Free
AZ100EL16VOU+
AZH+
16VOU
1,2,4
DIE
AZ10/100EL16VOXP N/A
5
DIE
AZ10/100EL16VOXR N/A
6
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel.
2 Date code format: “Y” or “YY” for year followed by “WW” for week.
3 Parts marked JNB for date codes prior to 4WW (prior to 2004).
4 Date code “YWW” or “YYWW” on underside of part.
5 Waffle Pack. Die thickness 180 μm.
6 Die on 7 inch Tape & Reel, 3k parts per reel. Die thickness 180 μm.
June 2007 * REV - 23
www.azmicrotek.com
2




 AZ100EL16VO
AZ10EL16VO
AZ100EL16VO
TRUTH TABLE
E¯N¯ Q/Q¯
LOW or NC
HIGH
Data
Data
NC = No Connect
QHG
Data
LOW
HG
Data
HIGH
TIMING DIAGRAM
D
EN
Q
QHG
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
VCC
VI
VEE
VI
VI_DIFF
IOUT
PECL Power Supply
PECL Input Voltage
ECL Power Supply
ECL Input Voltage
Differential Input Voltage
Output Current
(VEE = 0V)
(VEE = 0V)
(VCC = 0V)
(VCC = 0V)
D/D¯
— Continuous
— Surge
TA Operating Temperature Range
TSTG Storage Temperature Range
1. VI_DIFF is the voltage difference between D and D¯
Rating
0 to +6.0
0 to +6.0
-6.0 to 0
-6.0 to 0
0 to ±1.6
50
100
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
Vpp1
mA
°C
°C
June 2007 * REV - 23
www.azmicrotek.com
3






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