SPP12N50C3 SPI12N50C3, SPA12N50C3
Cool MOS™ Power Transistor
Feature • New revolutionary high voltage technology • Ultra low gate charge
VDS @ Tjmax 560 V
RDS(on)
0.38 Ω
ID
11.6 A
• Periodic avalanche rated
PG-TO220-F3P-31 PG-TO262- PG-TO220
• Extreme dv/dt rated
2
• Ultra low effective capacitances • Improved transconductance
1 23 P-TO220-3-31
P-TO220-3-1
23 1
• PG-TO-220-3-31;-3-111: Fully isolated package (2500 VAC; 1 minute)
Type SPP12N50C3
Package PG-TO220
Ordering Code Q67040-S4579
Marking 12N50C3
SPI12N50C3 SPA12N50C3
PG-TO262 Q67040-S4578 PG-TO220FP SP000216322
12N50C3 12N50C3
Maximum Ratings Parameter
Continuous drain current
TC = 25 °C TC = 100 °C
Pulsed drain current, tp limited by Tjmax Avalanche energy, single pulse
ID=5.5A, VDD=50V
Avalanche energy, repetitive tAR limited by Tjmax2)
ID=11.6A, VDD=50V
Avalanche current, repetitive tAR limited by Tjmax Gate source voltage Gate source voltage AC (f >1Hz) Power dissipation, TC = 25°C Operating and storage temperature Reverse diode dv/dt 7)
Symbol
ID
ID puls EAS
EAR
IAR VGS VGS Ptot Tj , Tstg dv/dt
Value
SPP_I
SPA
11.6 7
34.8 340
11.61) 71) 34.8 340
0.6
0.6
11.6
11.6
±20
±20
±30
±30
125
33
-55...+150 15
Unit A
A mJ
A V W °C V/ns
Rev. 3.1
Page 1
2009-11-30
SPP12N50C3 SPI12N50C3, SPA12N50C3
Maximum Ratings Parameter Drain Source voltage slope
VDS = 400 V, ID = 11.6 A, Tj = 125 °C
Symbol dv/dt
Value 50
Unit V/ns
Thermal Characteristics Parameter
Thermal resistance, junction - case Thermal resistance, junction - case, FullPAK Thermal resistance, junction - ambient, leaded Thermal resistance, junction - ambient, FullPAK SMD version, device on PCB: @ min. footprint @ 6 cm2 cooling area 3) Soldering temperature, wavesoldering 1.6 mm (0.063 in.) from case for 10s 4)
Symbol
RthJC RthJC_FP RthJA RthJA_FP RthJA
Tsold
Values
Unit
min. typ. max.
-
-
1 K/W
-
-
3.8
-
-
62
-
-
80
-
-
62
-
35
-
-
- 260 °C
Electrical Characteristics, at Tj=25°C unless otherwise specified
Parameter
Symbol Conditions
Values
Unit
min. typ. max.
Drain-source breakdown voltage V(BR)DSS VGS=0V, ID=0.25mA 500
-
Drain-Source avalanche
V(BR)DS VGS=0V, ID=11.6A
-
600
breakdown voltage
-V -
Gate threshold voltage
VGS(th) ID=500µA, VGS=VDS 2.1
3
3.9
Zero gate voltage drain current IDSS
VDS=500V, VGS=0V,
µA
Tj=25°C
-
0.1
1
Tj=150°C
-
-
100
Gate-source leakage current
I GSS
Drain-source on-state resistance RDS(on)
VGS=20V, VDS=0V VGS=10V, ID=7A Tj=25°C Tj=150°C
-
- 100 nA
Ω
- 0.34 0.38
- 0.92 -
Gate input resistance
RG
f=1MHz, open drain
-
1.4
-
Rev. 3.1
Page 2
2009-11-30
SPP12N50C3 SPI12N50C3, SPA12N50C3
Electrical Characteristics, at Tj = 25 °C, unless otherwise specified
Parameter
Symbol
Conditions
Values
Unit
min. typ. max.
Characteristics
Transconductance
gfs
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance Crss
Effective output capacitance,5) Co(er)
energy related
Effective output capacitance,6) Co(tr) time related
VDS≥2*ID*RDS(on)max, ID=7A VGS=0V, VDS=25V, f=1MHz
VGS=0V, VDS=0V to 400V
-
8
-S
- 1200 - pF
- 400 -
-
30
-
-
45
-
-
92
-
Turn-on delay time Rise time Turn-off delay time Fall time
td(on)
VDD=380V, VGS=0/10V,
-
10
- ns
tr
ID=11.6A, RG=6.8Ω
-
8
-
td(off)
-
45
-
tf
-
8
-
Gate Charge Characteristics
Gate to source charge
Qgs
VDD=400V, ID=11.6A
-
5
- nC
Gate to drain charge
Qgd
-
26
-
Gate charge total
Qg
VDD=400V, ID=11.6A,
-
49
-
VGS=0 to 10V
Gate plateau voltage
V(plateau) VDD=400V, ID=11.6A
-
5
-V
1Limited only by maximum temperature 2Repetitve avalanche causes additional power losses that can be calculated as PAV=EAR*f.
3Device on 40mm*40mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70 µm thick) copper area for drain connection. PCB is vertical without blown air. 4Soldering temperature for TO-263: 220°C, reflow 5Co(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. 6Co(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 7ISD<=ID, di/dt<=400A/us, VDClink=400V, Vpeak