AZ10E131

www.DataSheet4U.com ARIZONA MICROTEK, INC. AZ10E131 AZ100E131 ECL/PECL 4-bit D Flip-Flop FEATURES PACKAGE AVAILABILITY 1100 MHz Min. Toggle Frequency PACKAGE PART NUMBER MARKING NOTES Differential Outputs AZM10E131 Individual and Common Clocks PLCC 28 AZ10E131FN 1,2 Individual Resets (asynchronous) AZM100E131 PLCC 28 AZ100E131FN 1,2 Paired Sets (asynchronous) Operating Range of 4.2V to 5.46V 1 Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel. 75kΩ Internal Input Pulldown Resistors 2 Date code format: “YY” for year followed by “WW” for week. Direct Replacement for On Semiconductor MC10E131 & MC100E131 DESCRIPTION The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CE ¯¯ n) inputs for clocking. Common clocking is achieved by holding the CE ¯¯ n inputs LOW and using CC to clock all four flip-flops. In this case, the CE ¯¯ n inputs perform the function of controlling the common clock to each flip-flop. Individual asynchronous resets are provided (Rn). Asynchronous set controls (Sn) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. Data enters the master when both CC and CE ¯¯ n are LOW, and transfers to the slave when either CC or CE ¯¯ n (or both) go HIGH. NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established. R3 D...