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AZV99 Dataheets PDF



Part Number AZV99
Manufacturers Arizona Microtek
Logo Arizona Microtek
Description PECL/LVDS Oscillator Gain Stage & Buffer
Datasheet AZV99 DatasheetAZV99 Datasheet (PDF)

www.DataSheet4U.com ARIZONA MICROTEK, INC. AZV99 PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable FEATURES • • • • • • • Green and RoHS Compliant / Lead (Pb) Free Packages Available Similar Operation as AZ100LVEL16VT except with LVDS Outputs Operating Range of 3.0V to 5.5V Minimizes External Components Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Available in a 2x2 or 3x3mm MLP Package S–Parameter (.s2p) and IBIS Model Files Available on Arizona Microtek Website P.

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www.DataSheet4U.com ARIZONA MICROTEK, INC. AZV99 PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable FEATURES • • • • • • • Green and RoHS Compliant / Lead (Pb) Free Packages Available Similar Operation as AZ100LVEL16VT except with LVDS Outputs Operating Range of 3.0V to 5.5V Minimizes External Components Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Available in a 2x2 or 3x3mm MLP Package S–Parameter (.s2p) and IBIS Model Files Available on Arizona Microtek Website PACKAGE MLP 8 (2x2x0.75) Green / RoHS Compliant / Lead (Pb) Free MLP 8 (2x2x0.75) MLP 8 (2x2x0.75) Green / RoHS Compliant / Lead (Pb) Free MLP 8 (2x2x0.75) Green / RoHS Compliant / Lead (Pb) Free MLP 16 (3x3) Green / RoHS Compliant / Lead (Pb) Free TSSOP 8 RoHS Compliant / Lead (Pb) Free DIE 1 2 3 4 PACKAGE AVAILABILITY PART NUMBER AZV99NG AZV99NA AZV99NBG MARKING V1G V9 V8G V2G AZMG V99 AZ+ V99 N/A NOTES 1,2 1,2 1,2 AZV99NDG 1,2 AZV99LG AZV99T+ AZV99XP 1,2 1,2,3 4 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel. Date code format: “Y” for year followed by “WW” for week. Date Code “YWW” on underside of part. Waffle Pack DESCRIPTION The AZV99 is a specialized oscillator gain stage with LVDS output buffer including an enable. The enable input (EN) allows continuous oscillator operation by only controlling the QHG /Q ¯ HG outputs. ¯ to VBB. The VBB pin can The AZV99 also provides a VBB and 470Ω internal bias resistors from D to VBB and D support 1.5 mA sink/source current. Bypassing VBB to ground with a 0.01 μF capacitor is recommended. MLP 16, 3x3 mm Package (L) or DIE (X) The MLP 16 and die versions of the AZV99 provide a selectable enable (EN). Enable polarity and threshold can be selected to accommodate either CMOS/TTL or PECL input levels. See the enable truth table for enable function. If enable pull-up is desired in the CMOS/TTL mode, an external ≤20kΩ resistor connecting EN to VCC will override the on-chip pull-down resistor. Outputs Q/Q ¯ each have a selectable on-chip pull-down current source. See the current source truth table for current source functions. External resistors may also be used to increase pull-down current to a maximum of 25mA (includes internal on-chip current source). 1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541 www.azmicrotek.com AZV99 MLP 8, 2x2 mm Package, NA, NB & ND Options The MLP 8 NA, NB and ND options of the AZV99 provide a PECL/ECL level enable input (EN ¯¯¯). When the ¯¯¯ EN input is LOW, the Q ¯ and QHG/Q ¯ HG outputs pass data from the inputs. When ¯¯¯ EN is HIGH, the Q ¯ output continues to pass data while the QHG output is forced high and the Q ¯ HG output is forced low. Only the Q ¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current source). The AZV99NB and AZV99ND versions operates with a single ended data input (D). The D ¯ input is internally bonded directly to the VBB pin bypassing the 470Ω bias resistor. TSSOP 8 Package (T), MLP 8 Package, (N) The TSSOP 8 (T) and MLP 8 (N) versions of the AZV99 provide a CMOS/TTL level enable input (EN). When the EN input is HIGH, the Q ¯ and QHG/Q ¯ HG outputs pass data from the inputs. When EN is LOW, the Q ¯ output continues to pass data while the QHG output is forced high and the Q ¯ HG output is forced low. Only the Q ¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current source). The TSSOP 8 (T) and MLP 8 (N) AZV99 operates with a single ended data input (D). The D ¯ input is internally bonded directly to the VBB pin bypassing the 470Ω bias resistor. NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established. PIN DESCRIPTION Q 4mA EA. PIN D/D ¯ Q/Q ¯ QHG/Q ¯ HG VBB EN-SEL EN/EN ¯¯ CS-SEL VEE VCC FUNCTION Data Inputs PECL Data Outputs LVDS Data Outputs Reference Voltage Output Selects Enable Logic Enable Input Selects Q and Q ¯ Current Source Magnitude Negative Supply Positive Supply Q D D 470 CS-SEL QHG QHG VBB VEE EN/EN CMOS/TTL THRESHOLD EN-SEL ENABLE TRUTH TABLE EN-SEL EN/EN ¯¯¯ Q/Q ¯ QHG Q ¯ HG CURRENT SOURCE TRUTH TABLE CS-SEL Q Q ¯ NC 4mA typ. 4mA typ. VEE1 8mA typ. 8mA typ. 0 4mA typ. VCC1 1 CS-SEL connections must be less than 1Ω. NC PECL Low or NC Data Data Data NC PECL High or VCC Data High Low CMOS/TTL Low, VEE or NC VEE1 Data High Low VEE1 CMOS/TTL High or VCC2 Data Data Data 1 EN-SEL connections must be less than 1Ω. 2 An external ≤20kΩ pull-up resistor between EN and VCC ensures a High when the EN pin is not driven. April 2007 * REV - 9 www.azmicrotek.com 2 AZV99 Absolute .


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