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U63716 Dataheets PDF



Part Number U63716
Manufacturers Simtek
Logo Simtek
Description CapStore 2K x 8 nvSRAM
Datasheet U63716 DatasheetU63716 Datasheet (PDF)

Obsolete - Not Recommended for New Designs www.DataSheet4U.com U63716 CapStore 2K x 8 nvSRAM Description The U63716 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In non-volatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U63716 is a static RAM with a non-volatile electrically erasable PROM (EEPROM) element incorporated in e.

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Obsolete - Not Recommended for New Designs www.DataSheet4U.com U63716 CapStore 2K x 8 nvSRAM Description The U63716 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In non-volatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U63716 is a static RAM with a non-volatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an integrated capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. The U63716 combines the ease of use of an SRAM with nonvolatile data integrity. STORE cycles also may be initiated under user control via a software sequence. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initiated by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. The U63716 is pin compatible with standard SRAMs and standard battery backed SRAMs. Features • • • • • • • • • • • • • • • • • • • CMOS non- volatile static RAM 2048 x 8 bits 70 ns Access Time 35 ns Output Enable Access Time ICC = 15 mA at 200 ns Cycle Time Unlimited Read and Write Cycles to SRAM Automatic STORE to EEPROM on Power Down using charge stored in an integrated capacitor Software initiated STORE Automatic STORE Timing 106 STORE cycles to EEPROM 100 years data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation Unlimited RECALL cycles from EEPROM Single 5 V ± 10 % Operation Operating temperature range: 0 to 70 °C -40 to 85 °C QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7) RoHS compliance and Pb- free Package: PDIP24 (600 mil) Pin Configuration Pin Description A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 VCC A8 A9 W G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 Signal Name A0 - A10 DQ0 - DQ7 E G W VCC VSS Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground PDIP 19 24 18 17 16 15 14 13 Top View March 31, 2006 STK Control #ML0053 1 Rev 1.0 U63716 Block Diagram EEPROM Array 32 x (64 x 8) STORE Row Decoder A5 A6 A7 A8 A9 SRAM Array 32 Rows x 64 x 8 Columns Store/ Recall Control VCC VSS RECALL Power Control VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Input Buffers Column I/O Column Decoder Software Detect A0 - A10 A0 A1 A2 A3 A4 A10 G E W Truth Table for SRAM Operations Operating Mode Standby/not selected Internal Read Read Write * H or L Characteristics All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage. E H L L L W * G * DQ0 - DQ7 High-Z High-Z Data Outputs Low-Z Data Inputs High-Z H H L H L * Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature a: Symbol VCC VI VO PD Min. -0.5 -0.3 -0.3 Max. 7 VCC+0.5 VCC+0.5 1 Unit V V V W °C °C °C C-Type K-Type Ta Tstg 0 -40 -65 70 85 150 Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. STK Control #ML0053 2 Rev 1.0 March 31, 2006 U63716 Recommended Operating Conditions Power Supply Voltage Input Low Voltage Input High Voltage Symbol VCC VIL VIH -2 V at Pulse Width 10 ns permitted Conditions Min. 4.5 -0.3 2.2 Max. 5.5 0.8 VCC+0.3 Unit V V V C-Type DC Characteristics Operating Supply Currentb Symbol ICC1 VCC VIL VIH tc VCC E W VIL VIH VCC W VIL VIH VCC E tc VCC E VIL VIH Conditions Min. = 5.5 V = 0.8 V .


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