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89HPES48T12 Dataheets PDF



Part Number 89HPES48T12
Manufacturers IDT
Logo IDT
Description 48-Lane 12-Port PCI Express Switch
Datasheet 89HPES48T12 Datasheet89HPES48T12 Datasheet (PDF)

www.DataSheet4U.com 48-Lane 12-Port PCI Express® Switch ® 89HPES48T12 Data Sheet Device Overview The 89HPES48T12 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES48T12 is a 48-lane, 12-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high-performance applications such as servers, storage, and communications/networking. It provides connectivity and switching functions between a PCI Express upstream port and up to.

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www.DataSheet4U.com 48-Lane 12-Port PCI Express® Switch ® 89HPES48T12 Data Sheet Device Overview The 89HPES48T12 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES48T12 is a 48-lane, 12-port peripheral chip that performs PCI Express packet switching with a feature set optimized for high-performance applications such as servers, storage, and communications/networking. It provides connectivity and switching functions between a PCI Express upstream port and up to eleven downstream ports and supports switching between downstream ports. ◆ Features ◆ High Performance PCI Express Switch – Twelve switch ports • Six main ports each of which consists of 8 SerDes • Each x8 main port can further bifurcate to 2 x4-ports – Forty-eight 2.5 Gbps embedded SerDes • Supports pre-emphasis and receive equalization on per-port basis – Delivers 192 Gbps (24 GBps) of aggregate switching capacity – Low-latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes ◆ ◆ – Supports one virtual channel and eight traffic classes – PCI Express Base Specification Revision 1.1 compliant Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin algorithms – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Supports locked transactions, allowing use with legacy software – Ability to load device configuration from serial EEPROM – Ability to control device via SMBus Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates forty-eight 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features – Redundant upstream port failover capability – Supports optional PCI Express end-to-end CRC checking Block Diagram x8/x4/x2/x1 SerDes DL/Transaction Layer Upstream Route Table Port Arbitration Scheduler 12-Port Switch Core Frame Buffer DL/Transaction Layer DL/Transaction Layer DL/Transaction Layer DL/Transaction Layer DL/Transaction Layer SerDes SerDes SerDes SerDes SerDes x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 48 PCI Express Lanes Up to 6 x8 ports or 12 x4 Ports Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 47 © 2007 Integrated Device Technology, Inc. July 19, 2007 DSC 6924 IDT 89HPES48T12 Data Sheet ◆ ◆ ◆ ◆ – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports optional PCI Express Advanced Error Reporting – Supports PCI Express Hot-Plug • Compatible with Hot-Plug I/O expanders used on PC motherboards – Supports Hot-Swap Power Management – Supports PCI Power Management Interface specification, Revision 1.1 (PCI-PM) • Supports powerdown modes at the link level (L0, L0s, L1, L2/L3 Ready and L3) and at the device level (D0, D3hot) – Unused SerDes disabled Testability and Debug Features – Built in SerDes Pseudo-Random Bit Stream (PRBS) generator – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters 32 General Purpose Input/Output pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions Packaged in a 35mm x 35mm 1156-ball Flip Chip BGA with 1mm ball spacing capacity through 48 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification 1.1. The PES48T12 is based on a flexible and efficient layered architecture. The PCI Express layers consist of SerDes, Physical, Data Link and Transaction layers. The PES48T12 can operate either as a store and forward switch or a cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable efficient switching and I/O connectivity. SMBus Interface The PES48T12 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES48T12, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES48T12 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 .


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