DatasheetsPDF.com

89PES5T5 Dataheets PDF



Part Number 89PES5T5
Manufacturers IDT
Logo IDT
Description 5-Lane 5-Port PCI Express Switch
Datasheet 89PES5T5 Datasheet89PES5T5 Datasheet (PDF)

www.DataSheet4U.com 5-Lane 5-Port PCI Express® Switch ® 89PES5T5 Data Sheet Advance Information* Device Overview ◆ The 89HPES5T5 is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports. ◆ ◆ Features ◆ ◆ High Performanc.

  89PES5T5   89PES5T5


Document
www.DataSheet4U.com 5-Lane 5-Port PCI Express® Switch ® 89PES5T5 Data Sheet Advance Information* Device Overview ◆ The 89HPES5T5 is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and up to four downstream ports and supports switching between downstream ports. ◆ ◆ Features ◆ ◆ High Performance PCI Express Switch – Five 2.5Gbps PCI Express lanes – Five switch ports – Upstream port is x1 – Downstream ports are x1 – Low-latency cut-through switch architecture – Support for Max Payload Sizes up to 256 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant Flexible Architecture with Numerous Configuration Options – Automatic lane reversal on all ports – Automatic polarity inversion – Ability to load device configuration from serial EEPROM Legacy Support – PCI compatible INTx emulation – Bus locking ◆ ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates five 2.5 Gbps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC motherboards Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Supports PCI Power Management Interface specification (PCIPM 1.2) – Unused SerDes are disabled. – Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state Testability and Debug Features – Built in Pseudo-Random Bit Stream (PRBS) generator – Numerous SerDes test modes – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters Block Diagram 5-Port Switch Core / 5 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler Transaction Layer Data Link Layer Transaction Layer Data Link Layer Transaction Layer Data Link Layer Transaction Layer Data Link Layer Transaction Layer Data Link Layer Mux / Demux Phy Logical Layer Mux / Demux Phy Logical Layer Mux / Demux Phy Logical Layer Mux / Demux Phy Logical Layer Mux / Demux Phy Logical Layer SerDes SerDes SerDes SerDes SerDes (Port 0) (Port 2) (Port 3) Figure 1 Internal Block Diagram (Port 4) (Port 5) IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 26 © 2007 Integrated Device Technology, Inc. *Notice: The information in this document is subject to change without notice September 7, 2007 Advance Information IDT 89PES5T5 Data Sheet ◆ ◆ 11 General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions Packaged in a 15mm x 15mm 196-ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express interconnect, the PES5T5 provides the most efficient I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 2.5 GBps (20 Gbps) of aggregated, full-duplex switching capacity through 5 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification revision 1.1. The PES5T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES5T5 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to allow efficient switching for applications requiring additional narrow port connectivity. North Bridge Memory Memory Memory Memory South Bridge x1 PES5T5 x1 GE LOM x1 GE LOM x1 GE x1 1394 Figure 2 I/O Expansion Application SMBus Interface The PES5T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES5T5, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES5T5 to be overridden following a reset .


89PES32T8 89PES5T5 92HD001


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)