CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKS™ CRYSTAL-TO-LVDS 312.5MH...
Description
www.DataSheet4U.com
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844101I-312
FEMTOCLOCKS™ CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
FEATURES
One 312.5MHz nominal LVDS output Selectable crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal or LVCMOS single-ended input Output frequency can be varied in 2% steps ± from nominal VCO range: 560MHz - 690MHz RMS phase jitter @ 312.5MHz, using a 25MHz crystal (1.875MHz-20MHz): 0.52ps (typical) Output supply modes Core/Output 3.3V/3.3V 3.3V/2.5V -40°C to 85°C ambient operating temperature Available in both standard and lead-free RoHS-complaint packages
GENERAL DESCRIPTION
The ICS844101I-312 is a low phase-noise frequency margining synthesizer and is a memHiPerClockS™ ber of the HiPerClockS™ family of high performance clock solutions from ICS. In the default mode, the device nominally generates a 312.5MHz LVDS output clock signal from a 25MHz crystal input. There is also a frequency margining mode available where the device can be programmed, using the serial interface, to vary the output frequency up or down from nominal in 2% steps. The ICS844101I-312 is provided in a 16pin TSSOP.
IC S
BLOCK DIAGRAM
OE CLK
Pullup Pulldown
PIN ASSIGNMENT
GND S_LOAD S_DATA Q S_CLOCK SEL nQ OE VDDA VDD 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MODE VDDO Q nQ GND CLK XTAL_OUT XTAL_IN
1
25MHz
÷P OSC
0
XTAL_IN XTAL_OUT SEL
Phase Detector
VCO
560 - 690MHz
÷N
Pulldown
÷M
ICS844101I-312...
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