ICS889832

www.DataSheet4U.com LOW SKEW, 1-TO-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER ICS889832 GENERAL DESCRIPTION The ICS889832 is a high speed 1-to-4 DifferentialIC S to-LVDS Fanout Buffer and is a member of the HiPerClockS™ HiPerClockS™ family of high performance clock solutions from IDT. The ICS889832 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF _AC pin allow other differential signal families such as LVPECL, LVDS, and SSTL to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes. The ICS889832 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in spaceconstrained applications. FEATURES Four differential LVDS outputs IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, SSTL 50Ω internal input termination to VT Output frequency: >2GHz Output skew: 25ps (maximum) Part-to-part skew: 200ps (maximum) Additive phase jitter, RMS: <0.2ps (typical) Propagation delay: 510ps (maximum) 2.5V operating supply -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM Q0 nQ0 IN 50Ω PIN ASSIGNMENT nQ0 Q1 1 nQ1 2 Q2 3 16 15 14 13 12 11 10 9 5 Q3 VDD Q0...