ICS9DBL411

www.DataSheet4U.com DATASHEET Four Output Differential Fanout Buffer for PCI Express Gen 1 & 2 Recommended Application: PCI-Express fanout buffer ICS9DBL411 Features/Benefits: Low power differential fanout buffer for PCIExpress and CPU clocks 20-pin MLF or TSSOP packaging Output Features: 4 - low power differential output pairs Individual OE# control of each output pair General Description: The ICS9DBL411 is a 4 output lower power differential buffer. Each output has its own OE# pin. It has a maximum input frequency of 400 MHz. Key Specifications: Output cycle-cycle jitter < 25ps additive Output to output skew: < 50ps Power Groups Pin Number (TSSOP) VDD GND 9,18 10,17 4 5 Pin Number (MLF) VDD GND 6,15 7,14 1 2 Description DIF(3:0) Analog VDD & GND Description DIF(3:0) Analog VDD & GND Funtional Block Diagram 4 OE#(3:0) 4 DIF_INT DIF_INC STOP LOGIC DIF_LPR(3:0) IDTTM/ICSTM Four Output Differential Buffer for PCI Express 1250A—07/31/07 1 ICS9DBL411 Four Output Differential Buffer for PCI Express Advance Information Pin Configuration OE0# DIF_INC DIF_INT VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR VDD_IO GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DIF0T_LPR DIF0C_LPR VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR OE2# DIF2T_LPR DIF2C_LPR 20-pin TSSOP ICS9DBL411 DIF0T_LPR DIF_INC OE0# 20 19 18 17 16 VDDA GNDA OE3# DIF3C_LPR DIF3T_LPR 1 2 3 4 5 15 14 13 12 11 VDD_IO GND OE1# DIF1T_LPR DIF1C_LPR 9DBL411 6 VDD_IO 7 GND 8 DIF2C_LPR 9 10 DIF2T_LPR OE2# 20-pi...