IDT74SSTU32D869

www.DataSheet4U.com IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 14-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32D869 FEATURES: 1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs Differential CLK input Control inputs compatible with LVCMOS levels Center input architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) Available in 150-pin CTBGA package APPLICATIONS: Along with CSPU877/A/D DDR2 PLL, provides complete solution for DDR2 DIMMs Optimized for DDR2-400/533 [PC2-3200/4300] Raw card L The SSTU32D869 is a 14-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32D869 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The SSTU32D869 includes a parity checking function. The SSTU32D869 accepts parity bits from the memory controller at its input pins PARIN[1:2], compares it with the data received on the D-inputs, and indicates whether a parity error has occured on its open-drain PTYERR[1:2] pins (active low). When used as a single device, the C1 inputs are tied low. In t...