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CY7C1294DV18 Dataheets PDF



Part Number CY7C1294DV18
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description (CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture
Datasheet CY7C1294DV18 DatasheetCY7C1294DV18 Datasheet (PDF)

www.DataSheet4U.com CY7C1292DV18 CY7C1294DV18 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture Features • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) @ 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize cl.

  CY7C1294DV18   CY7C1294DV18


CY7C1292DV18 CY7C1294DV18 CY7C1298F


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