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PC97551 Dataheets PDF



Part Number PC97551
Manufacturers Winbond Electronics
Logo Winbond Electronics
Description Embedded Controller
Datasheet PC97551 DatasheetPC97551 Datasheet (PDF)

www.DataSheet4U.com PC97551 Embedded Controller for Notebook Systems Product Brief February 2006 Revision 1.1 PC97551 Embedded Controller for Notebook Systems General Description The Winbond PC97551 is an embedded controller (EC) for mainstream notebook applications. It includes a highly optimized set of functions, which provide a hardware/firmware partition that enables the implementation of flexible solutions; and its high-performance CPU core enables EC functionality to be extended via the.

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www.DataSheet4U.com PC97551 Embedded Controller for Notebook Systems Product Brief February 2006 Revision 1.1 PC97551 Embedded Controller for Notebook Systems General Description The Winbond PC97551 is an embedded controller (EC) for mainstream notebook applications. It includes a highly optimized set of functions, which provide a hardware/firmware partition that enables the implementation of flexible solutions; and its high-performance CPU core enables EC functionality to be extended via the firmware. The PC97551 incorporates National’s CompactRISC CR16B core (a high-performance 16-bit RISC processor), internal ROM and RAM memories, system support functions and a Bus Interface Unit (BIU) that directly interfaces with both external memory (such as flash) and I/O devices. System support functions include: watchdog, PWM, timers, interrupt control, General-Purpose I/O (GPIO) with internal keyboard matrix scanning, PS/2® Interface, SMBus® interface, analog-to-digital (ADC) and digital-to-analog (DAC) converters for battery charging circuitry, system monitoring and analog controls. The PC97551 interfaces with the host via an LPC interface that provides the host with access to the Keyboard and embedded controller interface channels and to the BIOS flash. Like other members of Winbond’s Advanced I/O family, the PC97551 is PC01 and ACPI compliant. Outstanding Features ■ ■ ■ ■ ■ ■ ■ ■ Host interface, based on Intel’s LPC Interface Specification Revision 1.1, August 2002 PC2001 Rev 1.0, and ACPI 3.0 compliant 16-bit RISC core, with 2 Mbytes address space, running at up to 20 MHz Shared BIOS flash memory (external) 92 GPIO ports (including keyboard scanning) with a variety of wake-up events JTAG-based debugger interface Software and hardware controlled clock throttling and extremely low current consumption in Idle mode 176-pin LQFP and FBGA packages System Block Diagram South Bridge PWBTN Display Lid Switch Keyboard Mouse Touch Touch Pad Point SuperI/O LPC PCI TPM Wake-Up Enable ECSCI Sleep ON PWUREQ State Control SMI Brightness Contrast On/Off 4x PS/2 Internal Keyboard Keyboard Scan System Control and Status Switch Pad and LEDs Power Switch PCI Devices & Boards JTAG PWM PC97551 Beep Development Tacho Embedded Controller for Notebook Systems Control Direct CD Speaker EC Firmware, System BIOS Shared Flash Memory Local Bus ON and Switch Control Drv Drv Drv. Voltage Current AC Detect Voltage Current Voltage Temp. Player 2x SMBus Input Port Output Port Expansion GPIOs CPU Fans Temperature Power Supply Charger Battery AC Adaptor Temp. Sensor E2PROM Docking © 2006 Winbond Electronics Corporation www.winbond.com PC97551 www.DataSheet4U.com PC97551 Block Diagram LPC I/F Serial IRQ SMI Reset & Config CR16B Core Processing Unit DMA Host Controlled Functions LPC Bus I/F Core Bus I/F Functions CR Access Bridge Shared mem. + Protection Memory Bus Adapter RAM ROM BIU Internal Bus Peripheral Bus KBC + PM Host I/F Peripherals ACB (X2) PS/2 I/F Timer + WDG MFT16 (X2) MSWC HFCG ICU KBSCAN GPIO ADC USART PMC Valid Battery + Oscillator CLK MIWU Debugger I/F PWM DAC 32.768 KHz JTAG External Memory + I/O Features Embedded Controller ■ ■ ■ CompactRISC CR16B Processing Unit - a 16-bit embedded RISC processor core (the “core”) Internal Memory — Boot block for core code in 4 Kbytes of ROM — 4 Kbytes of on-chip RAM with contents protection — ROM and RAM both can hold code and data Bus Interface Unit (BIU) supporting: — Up to 2 Mbytes for code and data — Provides two chip-selects for flash/ROM and SRAM devices — Provides one chip-select for I/O devices — 8- or 16-bit wide bus — Configurable wait states — Enhanced performance using fast read cycles ❏ Single-cycle, fast-read (word-aligned) ❏ Operation Modes — IRE - Normal operation mode — OBD - On-Board Development mode ❏ Used for development in the final system ❏ ❏ Communicates with debugger via JTAG interface Hardware breakpoint support ■ — DEV - Development mode ❏ Used in In-System Emulators (ISE) and Application Development Boards (ADB) ❏ ❏ ❏ ■ Communicates with debugger via JTAG interface On-chip ROM is replaced with off-chip SRAM Cycle-by-cycle compatible with IRE mode Two-byte, burst-read (byte-aligned) — BIOS sharing with PC host — Host-core shared memory access protection ❏ Host-controlled with core override ❏ ❏ LPC System Interface — 8-bit I/O and 8-bit memory read and write cycles — 8-bit FWH read and write with wait-sync cycles — Bootable memory support — Base Address (BADDR) strap to determine the base address of the Index-Data register pair — Serial IRQ (SERIRQ) support — LPCPD and CLKRUN support 64-Kbyte and 8-Kbyte blocks with independent protection Hardware-protected boot zone for host code Core-Controlled Functions ■ — Download for on-board code updating ❏ Host-controlled via LPC ❏ Interrupt Control Unit (ICU) — Non-maskable interrupt input (PFAIL) — 31 maskable vectored interrupts — Enable and pending ind.


ABE0126 PC97551 QL63F5SA


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