500MSPS DACs. AD9781 Datasheet

AD9781 DACs. Datasheet pdf. Equivalent

Part AD9781
Description 500MSPS DACs
Feature Data Sheet FEATURES High dynamic range, dual DAC parts Low noise and intermodulation distortion Sing.
Manufacture Analog Devices
Datasheet
Download AD9781 Datasheet




AD9781
Data Sheet
FEATURES
High dynamic range, dual DAC parts
Low noise and intermodulation distortion
Single carrier W-CDMA ACLR = 80 dBc at 61.44 MHz IF
Innovative switching output stage permits usable outputs
beyond Nyquist frequency
LVDS inputs with dual-port or optional interleaved single-
port operation
Differential analog current outputs are programmable from
8.6 mA to 31.7 mA full scale
Auxiliary 10-bit current DACs with source/sink capability for
external offset nulling
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, RoHS compliant, 72-lead LFCSP
APPLICATIONS
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX
Wideband communications
LMDS/MMDS, point-to-point
RF signal generators, arbitrary waveform generators
Dual 12-/14-/16-Bit,
LVDS Interface, 500 MSPS DACs
AD9780/AD9781/AD9783
GENERAL DESCRIPTION
The AD9780/AD9781/AD9783 include pin-compatible, high
dynamic range, dual digital-to-analog converters (DACs) with
12-/14-/16-bit resolutions, and sample rates of up to 500 MSPS.
The devices include specific features for direct conversion transmit
applications, including gain and offset compensation, and they
interface seamlessly with analog quadrature modulators such as
the ADL5370.
A proprietary, dynamic output architecture permits synthesis
of analog outputs even above Nyquist by shifting energy away
from the fundamental and into the image frequency.
Full programmability is provided through a serial peripheral
interface (SPI) port. Some pin-programmable features are also
offered for those applications without a controller.
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals.
2. Proprietary switching output for enhanced dynamic
performance.
3. Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
CLKP
CLKN
LVDS
INTERFACE
D[15:0]
VIA, VIB
FUNCTIONAL BLOCK DIAGRAM
AD9783 DUAL LVDS DAC
INTERFACE LOGIC
SERIAL
PERIPHERAL
INTERFACE
INTERNAL
REFERENCE
AND
BIAS
GAIN
DAC
GAIN
DAC
OFFSET
DAC
OFFSET
DAC
16-BIT
I DAC
16-BIT
Q DAC
IOUT1P
IOUT1N
IOUT2P
IOUT2N
AUX1P
AUX1N
AUX2P
AUX2N
Figure 1.
Rev. C
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Tel: 781.329.4700 ©2007–2017 Analog Devices, Inc. All rights reserved.
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AD9781
AD9780/AD9781/AD9783
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Table of Contents .............................................................................. 2
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
Serial Peripheral Interface ......................................................... 19
REVISION HISTORY
8/2017—Rev. B to Rev. C
Changes to Table 12........................................................................ 22
6/2012—Rev. A to Rev. B
Changes to Table 2............................................................................ 4
Changes to Pins 25, 26, 29, and 30 Description, Table 6............. 7
Changes to Pins 9 to 24, 31 to 42, 25, 26, 29, and 30 Description,
Table 7 ................................................................................................ 8
Changes to Pins 25, 26, 29, and 30 Description, Table 7............. 9
Changes to SEEK Bit Function Description, Table 12............... 22
Changes to Parallel Data Port Interface Section......................... 25
Changed fDACCLK from 600 MHz to 500 MHz.............................. 26
Added BIST Operation Section .................................................... 27
Changes to Driving the CLK Input Section and Figure 59 ....... 27
Removed Evaluation Board Schematics Section ........................ 31
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
Data Sheet
General Operation of the Serial Interface............................... 19
Instruction Byte .......................................................................... 19
MSB/LSB Transfers .................................................................... 20
Serial Interface Port Pin Descriptions ..................................... 20
SPI Register Map ............................................................................ 21
SPI Register Descriptions .............................................................. 22
SPI Port, RESET, and Pin Mode ............................................... 24
Parallel Data Port Interface ........................................................... 25
Optimizing the Parallel Port Timing ....................................... 25
BIST Operation........................................................................... 27
Driving the CLK Input .............................................................. 27
Full-Scale Current Generation ................................................. 28
DAC Transfer Function ............................................................. 28
Analog Modes of Operation ..................................................... 28
Power Dissipation....................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
6/2008—Rev. 0 to Rev. A
Changed Maximum Sample Rate to 500 MHz Throughout .......1
Changes to Table 3.............................................................................4
Changes to Building the Array Section ....................................... 25
Changes to Determining the SMP Value Section ...................... 25
Added Evaluation Board Schematics Section............................. 30
Updated Outline Dimensions....................................................... 35
11/2007—Revision 0: Initial Version
Rev. C | Page 2 of 32







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