PowerTrench MOSFET. FDMS9600S Datasheet

FDMS9600S Datasheet PDF, Equivalent


Part Number

FDMS9600S

Description

Dual N-Channel PowerTrench MOSFET

Manufacture

Fairchild Semiconductor

Total Page 9 Pages
PDF Download
Download FDMS9600S Datasheet PDF


FDMS9600S Datasheet
FDMS9600S
Dual N-Channel PowerTrench® MOSFET
Q1: 30V, 32A, 8.5m: Q2: 30V, 30A, 5.5m:
May 2014
Features
General Description
Q1: N-Channel
„ Max rDS(on) = 8.5m: at VGS = 10V, ID = 12A
„ Max rDS(on) = 12.4m: at VGS = 4.5V, ID = 10A
Q2: N-Channel
„ Max rDS(on) = 5.5m: at VGS = 10V, ID = 16A
„ Max rDS(on) = 7.0m: at VGS = 4.5V, ID = 14A
„ Low Qg high side MOSFET
„ Low rDS(on) low side MOSFET
„ Thermally efficient dual Power 56 package
This device includes two specialized MOSFETs in a unique dual
Power 56 package. It is designed to provide an optimal
Synchronous Buck power stage in terms of efficiency and PCB
utilization. The low switching loss "High Side" MOSFET is com-
plemented by a Low Conduction Loss "Low Side" SyncFET.
Applications
Synchronous Buck Converter for:
„ Notebook System Power
„ General Purpose Point of Load
„ Pinout optimized for simple PCB design
„ RoHS Compliant
G1
D1
D1
D1 D1
G2
S2
S2
S1/D2
S2
Power 56
5 Q2
6
7
8
4
3
2
Q1 1
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDS
VGS
ID
PD
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
-Pulsed
Power Dissipation for Single Operation
TC = 25°C
TA = 25°C
TJ, TSTG
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 1a)
(Note 1a)
(Note 1b)
Q1 Q2
30 30
±20 ±20
32 30
12 16
60 60
2.5
1.0
-55 to +150
Units
V
V
A
W
°C
RTJA
RTJA
RTJC
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
Package Marking and Ordering Information
(Note 1a)
(Note 1b)
50
120
3 1.2
°C/W
Device Marking
FDMS9600S
Device
FDMS9600S
Package
Power 56
Reel Size
13”
Tape Width
12mm
Quantity
3000 units
©2008 Fairchild Semiconductor Corporation
FDMS9600S Rev.D2
1
www.fairchildsemi.com

FDMS9600S Datasheet
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Off Characteristics
BVDSS
'BVDSS
'TJ
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
ID = 250PA, VGS = 0V
ID = 1mA, VGS = 0V
ID = 250PA, referenced to 25°C
ID = 1mA, referenced to 25°C
IDSS
Zero Gate Voltage Drain Current
VDS = 24V, VGS = 0V
IGSS
Gate to Source Leakage Current
VGS = ±20V, VDS= 0V
Type Min Typ
Q1 30
Q2 30
Q1 35
Q2 29
Q1
Q2
Q1
Q2
Max Units
V
1
500
±100
±100
mV/°C
PA
nA
nA
On Characteristics
VGS(th)
'VGS(th)
'TJ
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
rDS(on)
Drain to Source On Resistance
gFS Forward Transconductance
Dynamic Characteristics
Ciss Input Capacitance
Coss
Output Capacitance
Crss Reverse Transfer Capacitance
Rg Gate Resistance
VGS = VDS, ID = 250PA
VGS = VDS, ID = 1mA
Q1 1 1.5
Q2 1 1.8
3
3
V
ID = 250PA, referenced to 25°C
ID = 1mA, referenced to 25°C
Q1
Q2
-4.5
-6.0
mV/°C
VGS = 10V, ID = 12A
VGS = 4.5V, ID = 10A
VGS = 10V, ID = 12A , TJ = 125°C
VGS = 10V, ID = 16A
VGS = 4.5V, ID = 14A
VGS = 10V, ID = 16A , TJ = 125°C
Q1
Q2
7.0 8.5
9.2 12.4
8.6 13.0
m:
4.5 5.5
5.3 7.0
5.4 8.3
VDD = 10V, ID = 12A
VDD = 10V, ID = 16A
Q1 54
Q2 68
S
VDS = 15V, VGS = 0V, f= 1MHz
f = 1MHz
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1280
2300
525
1545
80
250
1.0
1.7
1705
3060
700
2055
120
375
pF
pF
pF
:
Switching Characteristics
td(on)
Turn-On Delay Time
tr Rise Time
td(off)
Turn-Off Delay Time
tf Fall Time
Qg(TOT)
Total Gate Charge
Qgs Gate to Source Gate Charge
Qgd Gate to Drain “Miller” Charge
VDD = 10V, ID = 1A,
VGS = 10V, RGEN = 6:
Q1
VDD = 15V, VGS = 4.5V, ID = 12A
Q2
VDD = 15V, VGS = 4.5V, ID = 16A
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
13
17
23
31
ns
6
11
12
20
ns
42
54
67
86
ns
12
32
22
51
ns
9
21
13
29
nC
3
8
nC
2.7
6.5
nC
FDMS9600S Rev.D2
2 www.fairchildsemi.com


Features Datasheet pdf FDMS9600S Dual N-Channel PowerTrench® M OSFET FDMS9600S Dual N-Channel PowerTr ench® MOSFET Q1: 30V, 32A, 8.5m: Q2: 3 0V, 30A, 5.5m: May 2014 Features Gen eral Description Q1: N-Channel „ Max rDS(on) = 8.5m: at VGS = 10V, ID = 12A „ Max rDS(on) = 12.4m: at VGS = 4.5V, ID = 10A Q2: N-Channel „ Max rDS(on) = 5.5m: at VGS = 10V, ID = 16A „ Max rD S(on) = 7.0m: at VGS = 4.5V, ID = 14A Low Qg high side MOSFET „ Low rDS(on ) low side MOSFET „ Thermally efficien t dual Power 56 package This device in cludes two specialized MOSFETs in a uni que dual Power 56 package. It is design ed to provide an optimal Synchronous Bu ck power stage in terms of efficiency a nd PCB utilization. The low switching l oss "High Side" MOSFET is complemented by a Low Conduction Loss "Low Side" Syn cFET. Applications Synchronous Buck Con verter for: „ Notebook System Power „ General Purpose Point of Load „ Pino ut optimized for simple PCB design „ RoHS Compliant G1 D1 D1 D1 D1 G2 S2 S2 S1/D2 S2 Power 56 .
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