DatasheetsPDF.com

82C288 Dataheets PDF



Part Number 82C288
Manufacturers Intel Corporation
Logo Intel Corporation
Description BUS CONTROLLER
Datasheet 82C288 Datasheet82C288 Datasheet (PDF)

www.DataSheet4U.com M82C288 BUS CONTROLLER FOR M80286 PROCESSORS (M82C288-10 M82C288-8 M82C288-6) Military Y Provides Commands and Controls for Local and System Bus Wide Flexibility in System Configurations Implemented in High Speed CHMOS III Technology Fully Compatible with the HMOS M82288 Y Y Y Fully Static Device Single a 5V Supply Available in 20 Pin Cerdip Package (See Packaging Spec Order 231369) Y Y Y The Intel M82C288 Bus Controller is a 20-pin CHMOS III component for use in M80C.

  82C288   82C288


Document
www.DataSheet4U.com M82C288 BUS CONTROLLER FOR M80286 PROCESSORS (M82C288-10 M82C288-8 M82C288-6) Military Y Provides Commands and Controls for Local and System Bus Wide Flexibility in System Configurations Implemented in High Speed CHMOS III Technology Fully Compatible with the HMOS M82288 Y Y Y Fully Static Device Single a 5V Supply Available in 20 Pin Cerdip Package (See Packaging Spec Order 231369) Y Y Y The Intel M82C288 Bus Controller is a 20-pin CHMOS III component for use in M80C286 microsystems The M82C288 is fully compatible with its predecessor the HMOS M82288 The bus controller is fully static and supports a low power mode The bus controller provides command and control outputs with flexible timing options Separate command outputs are used for memory and I O devices The data bus is controlled with separate data enable and direction control signals Two modes of operation are possible via a strapping option MULTIBUS Compatible bus cycles and high speed bus cycles 20 Pin Cerdip Package 271077 – 2 Figure 2 M82C288 Pin Configuration 271077 – 1 Figure 1 M82C288 Block Diagram November 1991 Order Number 271077-006 www.DataSheet4U.com M82C288 Table 1 Pin Description The following pin function descriptions are for the M82C288 bus controller Symbol Type CLK I Name and Function SYSTEM CLOCK provides the basic timing control for the M82C288 in an M80286 microsystem Its frequency is twice the internal processor clock frequency The falling edge of this input signal establishes when inputs are sampled and command and control outputs change BUS CYCLE STATUS starts a bus cycle and along with M IO defines the type of bus cycle These inputs are active LOW A bus cycle is started when either S1 or S0 is sampled LOW at the falling edge of CLK Setup and hold times must be met for proper operation M80286 Bus Cycle Status Definition M IO 0 0 0 0 1 1 1 1 M IO I S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Interrupt Acknowledge I O Read I O Write None Idle Halt or Shutdown Memory Read Memory Write None Idle Type of Bus Cycle S0 S1 I MEMORY OR I O SELECT determines whether the current bus cycle is in the memory space or I O space When LOW the current bus cycle is in the I O space Setup and hold times must be met for proper operation MULTIBUS MODE SELECT determines timing of the command and control outputs When HIGH the bus controller operates with MULTIBUS I compatible timings When LOW the bus controller optimizes the command and control output timing for short bus cycles The function of the CEN AEN input pin is selected by this signal This input is typically a strapping option and not dynamically changed COMMAND ENABLE LATCHED is a bus controller select signal which enables the bus controller to resopnd to the current bus cycle being initiated CENL is an active HIGH input latched internally at the end of each TS cycle CENL is used to select the appropriate bus controller for each bus cycle in a system where the CPU has more than one bus it can use This input may be connected to VCC to select this M82C288 for all transfers No control inputs affect CENL Setup and hold times must be met for proper operation COMMAND DELAY allows delaying the start of a command CMDLY is an active HIGH input If sampled HIGH the command output is not activated and CMDLY is again sampled at the next CLK cycle When sampled LOW the selected command is enabled If READY is detected LOW before the command output is activated the M82C288 will terminate the bus cycle even if no command was issued Setup and hold times must be satisified for proper operation This input may be connected to GND if no delays are required before starting a command This input has no effect on M82C288 control outputs READY indicates the end of the current bus cycle READY is an active LOW input MULTIBUS I mode requires at least one wait state to allow the command outputs to become active READY must be LOW during reset to force the M82C288 into the idle state Setup and hold times must be met for proper operation The M82C284 drives READY LOW during RESET MB I CENL I CMDLY I READY I 2 www.DataSheet4U.com M82C288 Table 1 Pin Description (Continued) Symbol CEN AEN Type I Name and Function COMMAND ENABLE ADDRESS ENABLE controls the command and DEN outputs of the bus controller CEN AEN inputs may be asynchronous to CLK Setup and hold times are given to assure a guaranteed response to synchronous inputs This input may be connected to VCC or GND When MB is HIGH this pin has the AEN function AEN is an active LOW input which indicates that the CPU has been granted use of a shared bus and the bus controller command outputs may exit 3-state OFF and become inactive (HIGH) AEN HIGH indicates that the CPU does not have control of the shared bus and forces the command outputs into 3-state OFF and DEN inactive (LOW) When MB is LOW this pin has the CEN function CEN is an unlatched active HIGH input which allows the bus controller to activate its command and DEN outputs With .


Z646 82C288 82C288


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)