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®
1.0 Features
• Flexible DRAM banks configuration
- Supports 256K, 1M and 4M DRAM
• Block interleave mode operations
- Block interleaving at a block size of 512 bytes
• BIOS shadow RAM
- Shadow RAM for system, video and adapter BIOS
• Memory remapping
• Flexible multiplexed DRAM address
• Programmable AT bus clock
• Turbo switch
• 160-pin PQFP (Plastic Quad Flat Pack)
82C283
386SX System Controller
2.0 Overview
The 82C283 is a highly integrated, AT system logic VLSI chip
for high-end 386SX/AT systems. It integrates a local memory
controller (local memory is on-board memory), AT bus con-
troller, and data bus controller into one chip. It is designed for
systems running at 16MHz, 20MHz, 25MHz, and 33MHz*. A
high performance, compact 386SX/AT system is readily
implemented with the 82C283 and a standard peripheral con-
troller like OPTi’s 82C206 or the 82C100 (with Dallas Semi-
conductor (DS1287).
*Rev. B only
Figure 2-1 System Block Diagram
A Bus
D Bus
DRAM
RAS, CAS, SA Bus
MA
SD Bus
386SX
387SX
A[23:0]
D[15:0]
D[15:0]
XA0
A[16:1]
GA20
A[23:17]
A[9:1]
A[23:16]
OPTi
82C283
245
(x2)
245
OPTi
82C206
SD[15:0]
SA[19:17]
SA[16:0]
LA[23:17]
XD[7:0]
SD 245
XD[7:0]
SA
ROM
8042
September 1994
OPTi Inc. · 2525 Walsh Avenue · Santa Clara, CA 95051 · (408) 980-8178
