CY7C147

7c147: 12/4/89 Revision: Thursday, November 11, 1993 www.DataSheet4U.com Features D D D D D D D Automatic powerĆdown when deseĆ lected CMOS for optimum speed/power High speed Capable of withstanding greater than 2001V electrostatic discharge Ċ 25 ns Low active power Ċ 440 mW (commercial) Ċ 605 mW (military) Low standby power Ċ 55 mW TTLĆcompatible inputs and outputs The CY7C147 is a highĆperformance CMOS static RAMs organized as 4096 words by 1 bit. Easy memory expansion is provided by an active LOW chip enable (CE) and threeĆstate drivers. The CY7C147 has an automatic powerĆdown feature, reducing the power consumption by 80% when deselected . Writingtothedeviceisaccomplishedwhen the chip select (CE) and write enable Functional Description (WE) inputs are both LOW. Data on the input pin (DI) is written into the memory location specified on the address pins (A 0 through A 11). Readingthedeviceisaccomplished bytakĆ ingthechipenable(CE)LOWwhile(WE) remains HIGH. Under these conditions, the contents of the location specified on the address pins will appear on the data output (DO) pin. The output pin remains in a highĆimpeĆ dance state when chip enable is HIGH, or write enable (WE) is LOW. 4K x 1 Static RAM CY7C147 Logic Block Diagram Pin Configuration DIP Top View DI A0 A1 INPUT BUFFER A2 A3 A4 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VCC A6 A7 A8 A9 A 10 A 11 DI CE SENSE AMP A1 A2 A3 A6 A7 ROW DECODER A0 A5 DO 64 x 64 ARRAY DO WE GND C147Ć2 CE COLUMN...