MX98726

www.DataSheet4U.com ADVANCED INFORMATION MX98726 SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE 1.0 Features Direct interface to 80188/186 up to 40Mhz. Integrated 10/100 TP tranceiver on chip to reduce overall cost Fully comply to IEEE 802.3u spec. Best fit in network printer and hub/switch management application A local DMA channel between on-chip FIFOs and packet memory Shared memory architecture allow host and MX98726 to use only one single SRAM Host DMA can share packet memory with local DMA with simple hand shake protocol for x188/186 type of processor Support bus size configuration: - CPU : 8 bits, SRAM: 8 bits - CPU : 16 bits, SRAM: 8/16 bits Flexible packet buffer partition and addressing space for 32k, 64k up to 512 bytes NWAY autonegociation function to automatically set up network speed and protocol 3 loop back modes for system level diagnostics Rich on-chip register set to support a wide variety of network management functions Support 64 bits hash table for multicast addressing Support software EEPROM interface for easy upgrade of EEPROM content Support 1K bits and 4K bits EEPROM interface 5V CMOS in 128 PQFP package for minimum board size application 1.1 Introduction MX98726 ( Generic MAC , or GMAC ) is a cost effective solution as a generic single chip 10/100 Fast Ethernet controller. It is designed to directly interface 80188, 80186 ( host ) without glue logic. Two types of memory sharing schemes are supported, ...