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HY57V561620CT Dataheets PDF



Part Number HY57V561620CT
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 4 Banks x 4M x 16Bit Synchronous DRAM
Datasheet HY57V561620CT DatasheetHY57V561620CT Datasheet (PDF)

www.DataSheet4U.com HY57V561620C(L)T(P) 4 Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16. HY57V561620C(L)T(P) Series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the risin.

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www.DataSheet4U.com HY57V561620C(L)T(P) 4 Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620C(L)T(P) Series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620C(L)T(P) Series is organized as 4banks of 4,194,304x16. HY57V561620C(L)T(P) Series is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.) FEATURES • • • Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch (Leaded Package or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM Internal four banks operation • • • • Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst • - 1, 2, 4 or 8 for Interleave Burst Programmable CAS Latency ; 2, 3 Clocks • • ORDERING INFORMATION Part No. HY57V561620C(L)T(P)-6 HY57V561620C(L)T(P)-7 HY57V561620C(L)T(P)-K HY57V561620C(L)T(P)-H HY57V561620C(L)T(P)-8 HY57V561620C(L)T(P)-P HY57V561620C(L)T(P)-S Note : 1. HY57V561620CT Series 2. HY57V561620CLT Series : Nomal power & Leaded 54Pin TSOP II : Low power & Leaded 54Pin TSOP II Clock Frequency 166MHz 143MHz 133MHz 133MHz 125MHz 100MHz 100MHz Power Organization Interface 400mil 54pin TSOP II (Normal) / Low Power 4Banks x 4Mbits x16 LVTTL (Leaded) / Lead Free 3. HY57V561620CTP Series : Nomal power & Lead Free 54Pin TSOP II 4. HY57V561620CLTP Series : Low power & Lead Free 54Pin TSOP II This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5 / June 2004 1 www.DataSheet4U.com HY57V561620C(L)T(P) PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54pin TSOP II 400mil x 875mil 0.8mm pin pitch 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS PIN DESCRIPTION PIN CLK CKE CS BA0, BA1 A0 ~ A12 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE, UDQM and LDQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection RAS, CAS, WE UDQM, LDQM DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ NC Rev. 0.5 / June 2004 2 www.DataSheet4U.com HY57V561620C(L)T(P) FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 16 I/O Synchronous DRAM Self Refresh Logic & Timer Internal Row Counter CLK Row Active 4Mx16 Bank 3 CKE CS RAS CAS WE UDQM LDQM Row Pre Decoders 4Mx16 Bank 2 X decoders 4Mx16 Bank 1 X decoders 4Mx16 Bank 0 State Machine Column Active X decoders DQ0 DQ1 Sense AMP & I/O Gate X decoders Memory Cell Array I/O Buffer & Logic Column Pre Decoders Y decoders DQ14 DQ15 Bank Select Column Add Counter A0 A1 Address Register Address buffers A12 BA0 BA1 Mode Registers Rev. 0.5 / June 2004 Burst Counter CAS Latency Data Out Control Pipe Line Control 3 www.DataSheet4U.com HY57V561620C(L)T(P) ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Vol.


DEI1074 HY57V561620CT ESM4002


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