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IP2012 Dataheets PDF



Part Number IP2012
Manufacturers Ubicom
Logo Ubicom
Description (IP2012 / IP2022) Wireless Network Processor
Datasheet IP2012 DatasheetIP2012 Datasheet (PDF)

www.DataSheet4U.com PRELIMINARY March 17, 2003 IP2012 / IP2022 Wireless Network Processors Features and Performance Optimized for Network Connectivity 1.0 Product Highlights inexpensive product design and, when needed, quick and easy reconfiguration to accommodate changes in market needs or industry standards. The Ubicom IP2012™ and IP2022™ Wireless Network Processors combine support for communication physical layer, Internet protocol stack, device-specific application, and device-specific per.

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www.DataSheet4U.com PRELIMINARY March 17, 2003 IP2012 / IP2022 Wireless Network Processors Features and Performance Optimized for Network Connectivity 1.0 Product Highlights inexpensive product design and, when needed, quick and easy reconfiguration to accommodate changes in market needs or industry standards. The Ubicom IP2012™ and IP2022™ Wireless Network Processors combine support for communication physical layer, Internet protocol stack, device-specific application, and device-specific peripheral software modules in a single chip, and are reconfigurable over the Internet. They can be programmed, and reprogrammed, using pre-built software modules and configuration tools to create true single-chip solutions for a wide range of device-to-device and device-to-human communication applications. High speed communication interfaces are available via on-chip hardware Serializer/Deserializer (SerDes) blocks. These full-duplex blocks allow the IP2022 or IP2012 to be used in a variety of communication bridging applications. Each SerDes block is capable of supporting 10Base-T Ethernet (MAC and PHY), USB, GPSI, SPI, or UART. The highspeed operating frequency, combined with most instructions executing in a single cycle, delivers the throughput needed for emerging network connectivity applications. A flash-based program memory allows both in-system and runtime reprogramming. The IP2022 and IP2012 implement most peripheral, communications and control functions via software modules (ipModule™ software), replacing traditional hardware for maximum system design flexibility. This approach allows rapid, Key Features: • Designed to support single-chip networked solutions • Fast processor core • 64kB Flash program memory • 16kB SRAM data/program memory • 4kB SRAM data memory • Two SerDes communication blocks supporting common PHYs (Ethernet, USB, UARTs, etc.) and bridging applications (IP2012 has only one SerDes unit) • Advanced RISC processors • IP2022 — 120 and 160 MHz versions • IP2012 — 120 MHz version • High speed packet processing • Instruction set optimized for communication functions • Supports software implementation of traditional hardware functions • In-system reprogrammable for highest flexibility • Run time self-programmable • Vpp = Vcc supply voltage ipModuleTM Software Customer Application HTTP/SMTP/TFTP TCP/UDP IP/ICMP Network Access Layer PHY Firmware Choices for Communication: IP2022/IP2012 8/16-Bit Parallel Slave Port Internet Processor CPU 64-Kbyte Flash Memory ipOS Operating System 16-Kbyte Inst./Data RAM 4-Kbyte Data RAM External Memory Interface General Purpose I/O Ports Choices for Communication: ISA (802.11b) Mini-PCI/Cardbus (802.11g/802.11a) I2C General-Purpose I/O 10Base-T Ethernet (MAC/PHY on chip) USB 1.1 (SIE on chip) GPSI SPI UART/Modem Bluetooth HCI Host Bus 10Base-T Ethernet (MAC/PHY on chip) USB 1.1 (SIE on chip) GPSI SPI UART/Modem Bluetooth HCI High-Speed Serial Unit 1 (SERDES) 5 Timers PLL Clock Multiplier 8-Input 10-Bit A/DC ISP/ISD Interface High-Speed Serial Unit 2 (SERDES) 515-063b.eps Not available on IP2012 Figure 1-1 IP2012 / IP2022 Block Diagram www.ubicom.com © 2001-2003 Ubicom, Inc. All rights reserved. 1 www.DataSheet4U.com IP2012 / IP2022 Data Sheet 1 Additional Features. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.2 Serializer/Deserializers . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.3 Low-Power Support . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.4 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.6 Other Supported Functions . . . . . . . . . . . . . . . . . . . . . . .5 1.2.7 Programming and Debugging Support . . . . . . . . . . . . . . .5 2.0 Pin Definitions 6 2.1 PQFP (Plastic Quad Flat Package) for IP2022. . . . . .6 2.2 PQFP (Plastic Quad Flat Package) for IP2012. . . . . .7 2.3 µBGA (Micro Ball Grid Array) IP2022-120 Only . . . . .8 2.4 Signal Descriptions — IP2022 . . . . . . . . . . . . . . . . . .9 2.5 Signal Descriptions — IP2012 . . . . . . . . . . . . . . . . .12 15 3.0 System Architecture 3.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3.1 Loading the Program RAM . . . . . . . . . . . . . . . . . . . . . .19 3.3.2 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 3.4 Low Power Support . . . . . . . . . . . . . . . . . . . . . . . . .20 3.4.1 Clock Stop Mode (SLEEP) . . . . . . . . . . . . . . . . . . . . . .21 3.4.2 Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.5 Speed Change . . . ..


IP2022 IP2012 UPD78F9418A


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